Cadence PCB Best Practices

High Density Interconnect (HDI)

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High Density Interconnect Working with HDI October 2019 15 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Figure 1-7 Constraint Regions For more information, see the Differential Pair Constraint Data Sheets in the Allegro Platform Constraints Reference and Differential Pairs in the Constraint Manager User Guide. Via-in-Pad Overview Via-in-Pad is a common fanout strategy used on HDI designs, in particular on sub 0.5-mm BGAs. With Via-in-Pad, component placement can be more compact: Capacitors can be placed closer to the device pins they need to bypass. Via-in-pad also has its drawbacks, as it can introduce soldering issues in manufacturing. Solder can wick down through the open holes, if not plugged, drawing solder off the component pad. Different rules may exist for metal- and soldermask-defined pads. For metal-defined pads, a via should be contained within the SMD pad boundary; otherwise, the solderpaste spreads to include the via, resulting in possible tomb-stoning of components. With soldermask-defined pads, a via may be allowed to float within the SMD pad up to the point where the center of the via hole intersects the edge of the SMD pad. Typically, thru-hole vias are not allowed in SMD pads. Thru-hole vias can result in solderpaste flowing down the hole barrel. However, capabilities must exist to allow such conditions for thermal, RF shielding, and power applications.

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