High Density Interconnect
Working with HDI
October 2019 14 Product Version 17.4-2019
© 1999-2019 All Rights Reserved.
For more information, see the Analyze – Analysis Modes command in the Constraint
Manager Reference.
Same Net Spacing - DRC Markers
Same Net DRCs utilize the same letter codes as Net to Net, but lower case. For example, a
Net to Net via to via DRC is V-V; a Same Net DRC, v-v. The Constraint Manager – DRC
workbook lists Same Net DRCs.
For more information, see the Dictionary of DRC Error Marker Codes in the Allegro
Platform Constraints Reference and Same Net Spacing DRC Modes in the Constraint
Manager User Guide.
Etch Edit Support for Same Net Rules
Etch-editing integrates the bubble code (shove/hug) to allow it to work with certain Same Net
conditions. Sliding HDI vias in proximity with other vias or pins is more efficient due to the
adherence of Same Net rules. Other enhancements include:
■ Sliding of via stacks as a single entity
■ Splitting the stack (etch now connected to via, previously orphaned)
■ Sliding a via, then snapping it into a stack if rules permit
■ Adding HDI via structures while obeying Same Net Rules during insert
■ Staggered, Stacked, and Inset
■ Sliding of vias from pad will maintain etch connection (previously orphaned)
Constraint Regions
Same Net rules are supported in constraint regions. The following figure shows region-
defined rules for a Same Net SMD Pin to BB Via and Microvia. The blue font indicates values
that are directly set or an override state. These terms are used interchangeably. An override
supersedes values inherited from a CSet, and an override applies to all layers. If layer-based
settings are required, assigning a CSet is recommended.
