High Density Interconnect
Working with HDI
October 2019 18 Product Version 17.4-2019
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Figure 1-10 Via in Pad DRC Modes
For more information, see the Analyze – Analysis Modes command in the Constraint
Manager Reference.
Property Overrides
Not all packages may conform to a design-level check. It may be common to enable Via at
SMD Pin Fit as a design-level check, but certain packages may lend themselves to disabling
it. Specific properties are available for the Via at SMD Pin checks that override the design-
level check:
■ VIA_AT_SMD_Fit applied to pins or symbols
■ VIA_AT_SMD_ Thru applied to pins or symbols
For more information, see the Spacing and Same Net Spacing Data Sheets in the
Allegro Platform Constraints Reference.
For more information, see Constraint Overrides in the Allegro Platform Constraints
Reference.
HDI Via Structures
This methodology to add both conventional and HDI via structures includes a working layer
model based on the concept of multiple alternate layers, in conjunction with a via popup
interface. Double-clicking in the canvas displays the Via Popup interface, populated by the
layers enabled in the Working Layer Setup dialog box that displays along with access to the
via list.
