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The Most Common Low-Speed Serial Buses in PCBs

low speed serial buses

Back in the early days of computing, there was one simple method used to increase digital data transfer rates: expand the number of conductors in parallel. More conductors on a parallel bus meant more bits were flowing along the bus per second. As clock speeds and data rates increased, using wide parallel buses for transferring large amounts of data made less sense. You can save a lot of routing space, connector space, and I/O space with serial protocols, which transfer data at higher rates on a smaller number of conductors.

All high-speed protocols (with only a few exceptions in DDR and multi-lane PCIe) operate as differential serial protocols. However, even in systems that use serial digital protocols for high bandwidth communication, there will still likely be low-speed buses used to communicate with peripheral components. When most digital designers start their circuit board design careers, they will start by working with some of the low-speed serial buses presented in this article.

Common Low-Speed Serial Interfaces

All serial interfaces that run at low data rates have some common characteristics that distinguish them from high-speed differential interfaces:

  • They almost always use single-ended transmission lines
  • They might have a dedicated clock line or no clock at all
  • They have low clock rates (low MHz)
  • They do not have an impedance specification
  • They can be bidirectional with the addition of one wire

One thing that readers should note from this list: we said nothing about the edge rate for digital data in these buses! Why would that be the case?

The main point distinguishing a low-speed serial interface from a high-speed computing peripheral or serial standard (e.g., USB) is the data rate. We know, this is a bit confusing, especially because when we say “high speed” we are referring to the edge rate and not the clock frequency. What’s important to note is that, for some components or under certain bus design conditions, a low-speed serial interface can have a fast edge rate and can be regarded as operating near the edge of what would be considered “high speed”.

With that in mind, take a look at some of the capabilities of the three most common low-speed buses listed below. The protocols shown below are inter-integrated circuit (I2C), serial peripheral interface (SPI), and universal asynchronous receiver transmitter (UART). Unless you’re building with an interface for a legacy device, or unless you’re doing something more specialized like industrial systems.





Data/clock rate

Up to 3.4 MHz (High speed) or 5 MHz (Ultra-fast)

Up to 60 Mbps

Up to ~5 Mbps (there is no clock)

Edge rate depends on:

Pull-up resistor value, bus capacitance

Chip slew rate limit, bus capacitance

Chip slew rate limit

Conductor count

2 (bidirectional)

At least 3

2 (bidirectional)


Not recommended

Only series match at fast edge rates


Bus type




This is not an exhaustive list of serial protocols, but these three are definitely the most commonly used for communication between digital components. There are some other serial standards that operate over differential pairs at low speed (RS-485 and CAN). Whenever you need to operate at higher data rates, you will be working with a differential signaling standard.

Routing Recommendations for Low-Speed Buses

Even though these protocols are not operating with a defined impedance specification, it is still best to implement some basic high-speed PCB design practices for these buses. The design guidelines listed below are meant to prevent noise/EMI and to help prevent crosstalk

  • Make use of ground near signals to apply shielding and ensure a clear return path
  • Do not place excessive length mismatch between symbols on clocked buses
  • Note that these buses can produce crosstalk, so apply minimal spacing
  • Prefer the use of a ground plane, although ground pour is acceptable in 2-layer boards

Note that things like limiting vias and via stubs are not necessary. Line length limits are also not necessary, even in large boards. The reasoning is simple: the bandwidth of these signals is confined to low frequencies where losses are very low, so losses on these protocols are generally ignored.

In the event there is some source of loss that is problematic, a buffer or level shifter component might be useful for re-amplifying the signal or simply increasing the logic level nearer the driver end of the bus. Buffers have other useful functions

Front-end engineering and design work, as well as routing for low-speed serial buses, is much easier when you use the best PCB design tools in OrCAD, the industry’s best PCB design and analysis software from Cadence. OrCAD users can access a complete set of schematic capture features, mixed-signal simulations in PSpice, and powerful CAD features, and much more.

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