About 30 years ago, high data rate buses switched from parallel to serial. These buses were made possible by higher clock frequencies in processors and ASICs, and sending data as a serial transmission reduced the size of a bus to just a few wires. The extremely high data rate buses, such as USB or PCIe, are all serial bit streams that use an embedded clock. There are some that use source-synchronous clocking such as in MIPI standards.
For slower buses that use serial transmission over multiple conductors, the clocking mechanism is also source-synchronous. This is seen on the two most common single ended serial buses: I2C and SPI. In these Source-synchronous buses, there is an important timing constraint that ensures and interface can toggle on its logic states. This is known as the setup and hold time.
What is Setup and Hold Time?
The setup and hold time is a timing condition on a source-synchronous interface with respect to the incoming clock and data. Clock and data are sent on different conductors within a time window, and they arrive at the receiving interface ideally at the same instant. Once the clock and data arrive, the receiver can read the data coming into the bus at the clock frequency.
Sometimes, there is some ringing or noise on the data signal. The data could exhibit some oscillation that, in extreme cases, takes up a significant amount of the noise margin in the receiver’s buffer. In another instance, such as if the bus is intentionally slowed with series resistors, the rise time for a signal could be quite slow. In either case, the received signal needs to settle out to a final value before the clock arrives.
This is where we have setup and hold time. The setup and hold time on an interface is the time interval within which an incoming data signal must settle to its intended logic value before the incoming clock signal on the source-synchronous bus. Setup and hold times vary by interface: specialty logic could have a different setup and hold time than SPI. A much slower open drain bus like I2C is much less likely to exhibit these problems with settling from a transient oscillation, but it should still rise to its intended logic value within the setup and hold time.
We have two different times in this source-synchronous bus:
The setup time, referring to the time before rising clock edge
The hold time, referring to the delay between falling clock edge and data switching
When the interface does not obey these times, data in a bus might not be read correctly.
In summary, setup time refers to the time at which the clock can change, and hold time refers to the time at which the data can change.
How to Determine Setup and Hold Times
Setup and hold times for an interface and a component depend on the construction of a component and it is determined from measurements. You would have to measure the time between data and clock at which the interface starts to experience timing errors. The semiconductor manufacturer will do this for you. The value will then be specified in the component datasheet.
The example below comes from the STM32 datasheet. If you just search the datasheet for “setup” then you will find this table, which details many of the important timing specifications in the device.
If you look across multiple components, these delays between clock and data are not universal, meaning there is no single setup and hold time values that are common to all components.
How to Prevent Setup and Hold Time Errors
To ensure data is read correctly at a system peripheral, a delay is normally imposed between clock and data. On a PCB, if you had perfectly matched lengths for all the clock and data traces in your bus, you would still need to apply a delay. This can be done in your firmware by changing the value of one of your system variables. The value for that variable will be loaded into a register which will then impose the delay time between the clock and data.
The reason this is done in the application and not on a PCB has to do with the propagation speed of signals on a PCB. Signals on a PCB travel multiple many inches per nanosecond. Using the setup time for the STM32 listed above, manually tuning a trace to apply the required setup delay would mean that your clock trace requires an additional 36 inches of length! Obviously, this is not useful on small circuit boards, so we would prefer to apply any required delays in the device firmware.
Solve your setup and hold timing in firmware.
Programming firmware is just one part of the entire electronics development process that you can manage with the best PCB design features in OrCAD from Cadence. If you’re ready to take even more control over net logic and board layout, you can graduate to Allegro PCB Designer for a more advanced toolset and additional simulation options for systems analysis. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.