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How to Use an I2C Buffer in a PCB

I2C buffer

Just about every microcontroller, even small power-conservative components, implement the Inter-Integrated Circuit (I2C) serial bus interface. I2C is useful for connecting many low-speed peripherals on a motherboard or embedded system. These interfaces use a 7-bit addressing scheme that allows multiple masters to control multiple peripherals over a simple 2-wire bus.

When designing a PCB, sometimes a buffer is required due to the physical size of the bus becoming so large. An I2C buffer is like a kind of repeater, but it is not meant to overcome the loss on the bus. Due to the typically slow rise times of an I2C bus, these buses do not experience signal degradation due to losses as you would see in a high-speed digital bus. Instead, they restore the timing characteristic to some desired level so that the size of a bus can be made larger as needed.

I2C Bus Electrical Characteristics

The I2C bus consists of two active wires: the serial clock (SCL) and serial data (SDA) lines. Both of these lines are connected to pins on a master controller or peripheral ASIC, both of which are open-drain pins that require pull-up resistors. This means either the master or a peripheral device can pull the SDA line low, while the pull-up resistor passively returns the lines to a high voltage level, which toggles all logic states.

There are two key electrical parameters that affect I2C bus performance include:

  • Bus capacitance (Cbus) - Higher capacitance of the SCL and SDA traces and all input pins on devices connected to the bus increases the rise time of a data signal and clock edge.

  • Pull-up resistors (R) - A resistor is connected between SCL/SDA and VCC. A lower resistor value reduces rise time but increases current flowing through the open drain (higher power consumption).

Typical values used in an I2C bus for the pullup resistor are 10 kOhms. As an example, if we have a total bus capacitance of 100 pF, the 10%-90% rise time for an SCL/SDA signal would be approximately 2.2 microseconds. This is calculated easily by considering the I2C bus to essentially be a charging/discharging RC circuit. The bus would look like the image shown below.

I2C buffer

As more devices are added to the I2C bus, the value of Cbus increases due to the load capacitance of each device and the additional trace capacitance. Eventually, the total capacitance will reduce the maximum I2C clock speed that can be reliably supported. The higher bus capacitance can be offset with a smaller pull-up resistor, but the smaller resistor increases the power consumption via the open-drain pin. Some drain currents might be limited to only a few mA, which is why pull-up resistor values should be around 10 kOhms.

Slow rise times can also cause timing problems if they exceed the I2C device’s input threshold region. This could lead to misinterpreted voltage levels during the interface’s timing window. Because 

Enter the I2C Buffer

To illustrate why I2C buffers are needed, let’s consider an example. Suppose we have a board with two I2C devices, a microcontroller and an EEPROM. The microcontroller acts as the I2C master and the EEPROM is a peripheral device.

At the fast-mode clock speed of 400 kHz, the master can access data from the EEPROM correctly with no timing errors. But if several more peripheral ICs are added to the board, the bus eventually stops working. These extra devices add capacitance to the existing bus. Because these devices are all added to the bus in parallel, the increased capacitance starts to cause slow rise times on all devices on the bus, and eventually there are communication errors.

There are two main ways to address I2C bus performance limitations:

  • Lower pull-up resistor values - Using smaller resistors reduces rise times but greatly increases power consumption by increasing the drain current.

  • Lower the I2C clock speed - This increases the timing margin on the rising edge of the SCL/SDA signals, but it also reduces throughput.

  • Add I2C buffers/repeaters - An I2C buffer splits the bus into multiple smaller segments that can be driven independently with the buffer.

An I2C buffer and its bus connections have the structure shown below.

I2C buffer

Implementing I2C Buffers in a PCB Design

I2C buffers allow designers to divide a large bus into smaller segments. This minimizes capacitance on each section. With lower capacitance, the pull-up resistor values can be increased to reduce I2C power consumption while still meeting rise time requirements.

An I2C buffer can also provide level shifting capabilities that will step up or step down signals between segments. This allows a high-voltage device to communicate with a lower voltage device, but both supply voltages will need to be added to the PCB.

When designing a PCB, consider adding an I2C buffer or repeater if:

  • The I2C bus has high capacitance from many devices

  • SDA/SCL rise times are too slow due to large pull-up resistors

  • The I2C devices require different signal levels

  • The I2C devices require different clock frequencies

  • The I2C devices have different pull-up resistor limits

  • Communication errors occur at higher bus speeds

Some benefits of using I2C buffers include:

  • Divide large bus into smaller segments to reduce capacitance

  • Boost rise times by minimizing resistor values on each segment

  • Enable higher I2C clock speeds compared to a single long bus

  • Prevent propagation delays from impacting bus timing

  • Isolate electrical noise between bus segments

Properly incorporating I2C buffers early in the design process can ensure robust performance as more functionality is added to the PCB later. This prevents reliability issues and avoids costly redesigns. It also allows for a simple method to extend I2C signaling across multiple boards if needed, which might be sent over a cable or FPC ribbon.

Where to Place I2C Buffers

When laying out a PCB with multiple I2C devices, there are a few effective ways to place I2C buffers:

Separate clusters of devices into I2C segments. If certain I2C devices are physically grouped together on the board, placing a buffer between the clusters isolates them into separate bus segments. This contains capacitance within each group.

Place buffer near the middle of the bus. Putting a buffer midway down a long bus helps split capacitance evenly on both segments. This way the buffer sees/creates similar rise times on each side of the bus.

Place a buffer near devices with very high capacitance. If a few of the peripheral devices have larger capacitance, they can be placed on the output side of a buffer so that they do not slow down the rest of the bus.

Use multiple cascaded buffers to divide a complex bus. For a bus with many devices spread over a large area, cascading 2-3 buffers splits the bus into several low-capacitance segments for better performance.

I2C Buffer as a Backup Bus

Another option for using an I2C buffer is as a backup bus, which essentially creates a redundant bus over which a master device can communicate. If there is some chance of failure along the bus, then the buffer could be enabled in order to turn on a backup component or peripheral. This type of system would be seen in a high reliability application, such as power electronics for infrastructure or in industrial systems.

This use of buffers is used when the chances of a device failure can cripple an entire system. The failure of a single device on a bus can be overcome by placing a redundant circuit on the bus that is separated with a buffer. The buffer can then be enabled by switching on its power or toggling its ENABLE/SHDN pin.

I2C buffer

In this case, a control method is needed to sense the protected device and determine whether the device has failed. If the device has failed, the master controller can switch over to the protected bus by toggling the enable pin. This requires some additional effort in an embedded application, but the redundant bus ensures long-term reliability of the system.

When you’re ready to design a custom PCB with I2C buffers for your next product, make sure your company uses the best PCB design features in OrCAD from Cadence. If you’re ready to take even more control over net logic and board layout, you can graduate to Allegro PCB Designer for a more advanced toolset and additional simulation options for systems analysis. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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