PLL vs. DLL: wWhich is best for clock synchronization?
Modern memories, telecommunications devices, and other systems that require precise signal timing make copious use of synchronization methods. Among the various methods for applying synchronization between signal lines and a reference clock, phase-locked loops (PLLs) and delay-locked loops (DLLs) are arguably the most popular. Here’s what you need to know about PLLs vs. DLLs and how to work with these devices in your digital or analog system.
PLL vs. DLL Functions and Design
PLLs and DLLs operate in a similar function, but they are used for different applications. Both types of circuits operate with a feedback loop. The goal is to lock the phase of an output signal train to some reference signal, ensuring the two signals are very precisely timed. This is particularly important in digital systems that run at high data rates with fast clock/signal edges. The two components differ only slightly in terms of how they synchronize system and signal clocks.
A PLL uses a highly stable VCO (or an NCO for digital PLLs), and the phase of the VCO is fed back to the input of the circuit. A phase detector and loop filter are then used to regenerate a clock train from the VCO. PLLs typically provide frequency multiplication, which allows a faster or slower clock train to be generated from the input system clock. In contrast, a DLL typically does not provide frequency multiplication, although research into this area is ongoing. A DLL simply uses an adjustable delay line to align the output clock pulse and the reference clock pulse.
PLL applications include removing phase differences between the output and reference clock signal (clock deskewing), clock recovery from a random data stream (e.g., in a serial-link receiver), amplitude demodulation, and frequency synthesis.
Block diagrams for PLL vs. DLL circuits
The primary application for a DLL is deskewing. Propagation delay accumulates when a clocking signal travels on interconnects, traverses buffers and gates, or is in some other way delayed throughout the system. You can use a DLL to remove skew and synchronize the phase of a system clock before feeding it to multiple components. This ensures these components receive clock pulses that are in-phase, ensuring these components remain synchronized.
Notice the feedback connection point in the figure below; feedback is sent from the downstream unit (ILU, IC, or other component) back to the DLL. The timing of the output clock pulses are adjusted slightly to compensate any phase difference between the system clock and the downstream clock pulse trains.
These DLLs ensure that the clock signals at all downstream elements are in-phase.
PLLs and DLLs in Your PCB Layout
DLLs and PLLs will generally be included in SoCs, processors, or other components that need them to operate properly. You may not even see the output from these integrated components unless you are working with a system that requires source-synchronous clocking (e.g., SDRAM). As long as you follow the component manufacturer’s layout recommendations, your board should work properly.
PLLs can also be brought into your layout from discrete components, or as its own integrated circuit. The former applies to DLLs; you can use COTS components to build a custom DLL directly on your board. Design of DLLs packaged in their own integrated circuits, and design of DLLs as frequency multipliers, is still an active area of electronics research. A related area of research is the design of fully differential PLLs and DLLs.
PLL ICs are not used for source-synchronous clocking, as the PLL in this particular application is built into the relevant source component. In the case of source-synchronous clocking, you’ll need to carefully match the lengths of signal traces with your output clock pulse so that the receiver component latches to the incoming data on the rising clock edge. Precise timing is critical in these systems, so skew should be minimized as much as possible.
In other applications, a PLL IC is used as a stable reference clock in applications that require very precise timing. A perfect example is time-to-digital conversion in rangefinding, where a small amount of jitter in the receiver component can translate into a huge error in distance measurements. In this particular application, the pulse train that drives your transmitter (such as a laser diode, piezoelectric transducer, or radar emitter) can contain jitter, meaning the pulse train is no longer perfectly in phase with the receiver clock. A PLL IC can be used to generate a new reference clock that is perfectly phase locked to the driving pulse train, which is then used to drive the receiver IC. This ensures the receiver and driver are in-phase and any jitter/delay is compensated. In transceiver SoCs, a DLL or a PLL can be used for this same purpose.
Example application for rangefinding with a PLL
PLL and DLL Circuit Design
On the circuit design side, PLLs and DLLs are rather easy to simulate. For PLLs, you’ll want to simulate phase locking and frequency multiplication in the time domain for various levels of delay between the input and reference signals. This will show you how the phase and frequency converge to the desired values over time. With DLLs, you’ll effectively be simulating the same aspects in the time domain, although you won’t generally be worried about frequency multiplication unless you are designing a new type of DLL circuit.
As PLLs can be used to output a high frequency multiple of the input clock signal on a single-ended line, it’s a good idea to check for crosstalk in your layout. It may be tempting to design interconnects on the low and high frequency sides of the PLL in the same way, but you should still check for crosstalk as its magnitude increases with frequency. You’ll also need to precisely design interconnects with controlled impedance values to prevent reflections at the receiver. Be sure to check your datasheets and signalling standards for termination requirements. These simulations can be done easily with some basic post-layout simulation tools.
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