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Contamination Delay in Clock Circuits: Best PCB Routing Techniques

Load output and propagation delay from Adler and Friedman



We currently are neck deep in the middle of the cold and flu season, and at our local elementary school there are a lot of children and teachers that are out sick. In fact, there are some school districts that have closed down schools temporarily because so many people are ill. To avoid further sickness, the school now smells like disinfectant as the staff continuously clean chairs, desks, and any other surface that might be contaminated.

I’m pretty sure that everyone has a very clear idea of what this type of contamination means, especially if you’re at home coughing up a lung while you are reading this. But when working with clock circuits on your design, there is another version of contamination to deal with that has nothing to do with catching a cold; contamination delay. Here you will be balancing the amount of time that it will take to register the change in output logic after a change to the input. Let’s take a closer look at what contamination delay in clock circuits is, and how that will affect your PCB layout.

What is Contamination Delay in Clock Circuits?

There can be some confusion when talking about delay in clock circuits. On one hand “propagation delay” is what PCB designers deal with in layout when routing traces. This is the amount of time that it takes for the signal to travel through a transmission line from the source to the target. It is essential that good trace routing techniques are used on a printed circuit board so that the clocks and other signals will arrive simultaneously and work together seamlessly as they are designed to. We will talk more about that in a moment. Propagation delay however is also used in combination with “contamination delay” to describe the switching time effects within logic circuits.

When a clock signal edge triggers a logic device, the two delays define the amount of time it takes for the outputs to change value. Contamination delay is the minimum time required after a change to the input before the output begins its initial change. Propagation delay, on the other hand, is the maximum amount of time needed for the output to finish its change in value. Knowing these delay values, which are measured in picoseconds and nanoseconds, is important in ensuring that you have the correct setup and hold times in your logic so the inputs are stable when the clock edge arrives.

Digital circuitry will usually contain multiple components which when combined together will create sequential circuits. By using the different delay parameters of the sequential logic components, you can calculate the maximum clock frequency at which your circuits will generate the best results. There are different reasons for these delays including capacitance in the circuit, differences in operating speed between multiple inputs and outputs, and the operating temperature of the circuit. The manufacturers of the components that you are using will normally provide the delay values for their devices in the part data sheets, which you can then use for your calculations.


 Screenshot of OrCAD 3D layout routing patterns

To get trace routing at the right length, serpentine routing patterns will be used


Keeping it Clean with Good Clock Routing Techniques

Once your clock circuits are engineered to be at their best operational performance, that work can still be undone if the clock circuits aren’t routed correctly on the printed circuit board. These nets are noisy and must be protected, and they must be routed in precise patterns and at specific lengths.

To reduce the impact of a noisy clock circuit from the rest of the board, it is a good practice to locate clock circuitry towards the center of the PCB as opposed to the edges. You also will want to place your components so that different clock routing doesn’t cross over each other. Using power and ground layers adjacent to your routing layers to shield your clock lines is also important. Make sure that your clock traces have good clean return paths on the planes, and don’t route them over any plane splits which would ruin the integrity of the return path. A good rule of thumb is to maintain a spacing of 3 times the trace width between clock lines and other routing.

The purpose of the clock is to provide timing for the printed circuit board circuitry, and thereby coordinate the activity that is going on within the circuits. With memory circuits, the clock pulse will trigger the inputs and outputs of data, and therefore must be timed so that each bit of data arrives and stabilizes before the next clock cycle. To do this means that both the clock and data lines must be routed to exact lengths. Since electrical signals can’t be sped up, the only option is to add length to the line to delay the signal arrival to match the arrival speed of the longest lines in the circuit. For clock lines with multiple receivers, you will want to route to the receiver that is the furthest away from the driver first, and then match that length when routing to the other recievers.


Screenshot of 3D PCB layout

Advanced PCB design tools will help you to route complex trace topologies


How Your PCB Design Tools Can Help

As you can see, there are a lot of specific routing rules and constraints that must be followed to correctly route a good clock line. The best thing that you can do to help yourself will be to use PCB design tools that will support these and other high speed design parameters. Most design tools today support general PCB design rules that will keep you from making errors, and the best tools will allow you to set up constraints for specific purposes. For instance, advanced high speed rules will allow you to set up routing lengths for nets, and flag any nets that don’t match those length rules. You will also have the ability to automatically add serpentine routing patterns to the trace routing in order to increase their length to the desired values.

To ensure your success in routing clock lines and other critical signals on your printed circuit board, you should use tools that have these abilities built into them. Thankfully the PCB design tools that you need for routing these sensitive signals are already available to you from the Cadence line of high performance EDA tools. OrCAD PCB Designer has the features that we’ve been talking about with high speed design constraints, matched length rules, and trace tuning to automatically route your clock lines to the correct length.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.