How to Prevent Clock Skew in PCB Design
If I were a superhero, my kryptonite would easily be my inability to arrive anywhere when I’m expected. I’m always running five minutes late, at least, and I’ve started having to give myself close to twenty or thirty additional minutes just to compensate for my inevitable lateness. I actually started, recently, purposefully setting my clock ten minutes forward to give me a more honest time assessment.
In PCB design, you expect clock signals to arrive promptly at its integrated circuits’ (IC) destination. However, a phenomenon termed clock skew can result in clocking signals arriving earlier or later at certain ICs. This, of course, causes inconsistencies to the data integrity of the respective ICs.
What Is Clock Skew
Clock skew is a phenomenon where clocking signals arrived at different destinations at varying intervals. Clocking signals are commonly used for synchronous communication in PCB design. For instance, the Serial Peripheral Interface (SPI) uses a clock signal to transmit and receive data between devices.
In an ideal master to multiple slave components configuration, there is no delay in the propagation time of the clock signal. All components connected on the clocking bus are expected to receive the signal at the same time.
However, in real life application, propagation delay happens and the clock pulse can arrive at various intervals to the destination components. The culprit of clock skew is parasitic capacitance and the differing trace length of the clock signals.
Imagine a clock signal that originates from a driver and splits into two different paths. Path A is half the length of path B, and they both connect to different receivers. It is only natural that the clock signals on Path A reach its destination earlier than the clock signal on Path B.
The difference between the arrival time of the clock signal and the receiving pins is the skew value.
How Clock Skew Affects PCB
In electronics, the clocking signal serves as a time reference for a component to latch the data bit on the receive pin. Some protocols latch the data on an upward clock pulse while others do so on a downward clock pulse. Regardless of the latching mechanism, a reliable clocking reference is important.
In the event of clock skew, the clocking signal may match earlier or later than intended. When the clock changes prior to the update in the data signal, the receiving component will latch the old data into its register. If the protocol latches data based on the clock steady state instead of transition, clock skew may result in the receiver overwriting the memory with two consequent data.
Generally, clock skew isn’t a problem with low-speed design as there is a generous margin of error. However, if you’re designing a high-speed application in the region of hundreds of MHz, clock skew becomes a real concern.
Clock skew is a significant issue in high speed design.
The latching error can result in serious corruption on data integrity and that can be disastrous in actual applications. Prevention is always better than cure when it comes to teething problems caused by clock skew.
Tips To Prevent Clock Skew In PCB Design
When you have understood the cause of clock skew, preventing the phenomenon becomes easier. The key to preventing clock skew lies in ensuring the clock signals arrive at the same time on different receivers.
To do that, you’ll want to ensure that the trace length between the source and destination component should be equal (length matched). This means that the shortest trace length may not be the best path anymore.
Equal trace length helps to prevent clock skew.
In a typical synchronous design, you’ll have one driver connected to several receivers. Chances are, some receivers will be closer to the driver and others will be further away on the PCB. You’ll want to route the clock signal to the furthest pin first and ensure the other clock signal trace are routed with the same length.
It is also important to avoid branches in the clock signal to prevent reflection. This can be done by using a clock driver instead of routing directly from the source component to the receivers. In addition, using impedance matching resistors on the clock signals also help to ensure the clock signal integrity.
You will want to consider using an advanced PCB design software to minimize clock skew issues. The Cadence PCB backend board layout software allows high-speed signal challenges to be identified and resolved in a timely manner.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.