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Power Integrity: The Backbone of Reliability

Key Takeaways

  • Power integrity can be understood best through the topics of impedance matching and max power transfer.
  • Decoupling capacitors act as local power storage units and filters.
  • Power plane design works hand-in-hand with placement to optimize performance.

Switching power circuit

Power integrity ensures the work that goes into design, placement, and routing is maximized.

Any design with a modicum of complexity has to appropriately account for the power systems that bring life to the circuit. Whether it’s a single source or multiple power nets, neglecting the power system is akin to overlooking the importance of a circulation system. Without proper power integrity safeguards in place, it is incredibly easy for a design to encounter significant runtime issues, both in the case of malfunction due to current starvation and fuzzy logic inputs creating indecipherable outputs.

Before diving into the meat of power integrity and how best to incorporate its best practices into designs, it's important to understand some of the underlying physics at work, starting with the topic of impedance matching and max power transfer.

The Physics of Power Integrity

Power integrity is a three-headed system comprised of (in order of increasing frequency response) the supply, decoupling capacitors, and the inherent capacitance of the IC package and dice. Designers and engineers must carefully take into account the frequency responses of the different ranges of the power system to craft an adequate filter effect. Impedance is a hugely important topic to power integrity, going all the way back to the power transfer function. At DC and other very low frequencies, power at the load is given by the equation:

Power at the load

This equation is derived from the alternate form of the power equation and Ohm’s Law. Max power transfer occurs when the resistance of the supply is equal to that of the load, or in other words, when the load and source resistance form a 1:1 voltage divider. However, nonidealized parasitics and most frequencies render a resistance model too narrow in scope. To properly account for these factors, designers must instead focus on the impedance profile of the circuit.

Impedance is a complex value consisting of both the real resistance (representing the signal’s magnitude) and imaginary reactance, which serves as a phase shift to a periodic signal. Given their similarities, the conditions for max power transfer also align such that:

Conditions for max power transfer

Z represents the impedance. The “*” represents the complex conjugate – if c is a complex number in the form of c = a + bi, then  c*= a - bi. Specifically, in terms of circuits, the complex value is indicated by the inductive or capacitive reactance, which is positive and negative, respectively. A complex value can be resolved into its pure magnitude by taking the square root of the sum of the squares of the real and imaginary components. Max power transfer occurs when this imaginary component sums to zero – essentially, impedance networks must provide an equal and opposite reactance value to negate the imaginary components of the impedance when summed. Thus, the idealized max power transfer in a purely resistive circuit is the specific case where the imaginary components of the source and load are zero.

Note that nowhere above (or indeed, for the remainder of the article) was efficiency mentioned, which may seem peculiar when discussing power. In fact, impedance matching is a highly inefficient method of power delivery, yet it has a very important role in the power system. Impedance matching can significantly reduce some deleterious effects such as voltage ripple and noise. Max power transfer ensures that what is delivered to the load is fully utilized to prevent some of the following issues:

  • Ground bounce - An instability condition that leads to a faulty state between a digital logic high and low. A base of a bipolar junction transistor (BJT) that has a poor connection to  ground (or alternatively, is unable to correctly register ground due to noise) may perceive the localized voltage increase in the region immediately surrounding the collector-emitter junction as reference. Due to the relatively large forward bias, this could mean that the base perceives its actual positive voltage as negative in reference to the heightened “ground”. This causes a shut-off of the BJT, which turns off the collector-emitter, allowing the process to continually repeat itself until the cessation of voltage on the base. Ground bounce can be especially troublesome due to its difficulty in diagnosis.
  • Electromagnetic interference - The more effective the power transfer at the load, the lower the intensity of reflected signals. In the case of power, reflected signals carry through the space between conductors (ground and power planes), which can cause pronounced EMI issues up to failure with compliance tests.
  • Additional concerns - Untransferred energy at the load eventually transforms to heat energy if it has no other avenue of transformation. In extremely dense designs, this can lead to early component or material wear, failure, and possible smoke and fire danger. Energy operating in particular frequencies of the electromagnetic spectrum may experience interference due to high-sensitivity equipment.

Decoupling Capacitors Fill Multiple Power Roles

Decoupling capacitors provide a wealth of functions to any properly operating power system. Indeed, designers with even the faintest layout experience have likely encountered them by the hundreds, if not thousands, in larger designs. Capacitors fill multiple roles within the realm of power design, but consider first the most basic of the component’s operation.

A capacitor, in the common water analogy of electronics, functions as a storage tank, except it contains charge instead of water. Depending on whether you ask a physicist or engineer, a capacitor is considered “full” (truthfully, a capacitor never fully charges or discharges) after four or five discrete cycles, known as the time constant. The time constant for a capacitor is directly related to the inherent resistance of the leads and the capacitance of the package such that:

Time constant for a capacitor

τ (tau) is the time constant. It’s fair to assume that within the same product lines and packages, resistance would be more or less constant. With that caveat, the charge and discharge time of a capacitor is driven foremost by its capacitance. In terms of a power system, this means the smaller farad capacitors are the quick-responding storage units filling in whenever the supply power dips. The layout designer should typically place these small decoupling capacitors as close as possible to the respective power and ground pins on ICs, as grouped in the schematic. This creates the smallest possible current loop, which is of extra importance when tied to the output of a fast-switching regulator. Progressively larger decoupling capacitors can be placed further away from the packages, as there is a less immediate need for a short, low impedance path between them and their respective pins.

This is not the only power function decoupling capacitors serve – in fact, the reason for their namesake has yet to be covered. Decoupling capacitors act as bandpass filters, allowing the passage of sufficiently high-frequency transients. This range rejects both DC and low-level frequencies as well as higher frequencies commonly associated with the high-speed range. Rejecting the DC impedes its flow across the capacitor, reinforcing the passage through the IC power and ground pins as the path of the least impedance. Alternatively, shunting AC frequencies within the range of operation helps protect the associated circuitry from any stray transients that may induce unintended operation or performance issues in the component.

Multiple SMT caps

For power integrity, there’s no such thing as too many decoupling capacitors.

Plane Design: From Stackup to Shapes

The design of power and ground planes collaborate to provide coverage across the board for direct current paths that minimize loop size. Poor or incomplete coverage can lead to significant EMI issues as well as unpredictable performance from the circuitry. There are many aspects to consider when discussing planes as they relate to power integrity, starting with the stackup.


The stackup is the physical orientation and designation of signal and plane layers on the z-axis. While the exact layer configuration can change depending on the needs of a particular board, it is common for plane layers to be paired in tandem. Most often, in a four-layer stack, placement and routing will occur on the outer layers while the inner layers are reserved for ground and power, respectively.

Ground and Power Planes

Ground planes form a consistent reference voltage for signal and power alike, while also ensuring return loops stay small to limit emissions. Power planes on the other hand are unlikely to occupy an entire layer, rather, some subdivision of complimentary plane shapes will ideally synergize with the layout in such a way that power shapes entirely encompass the net in question. In stacks of more multitudinous layer count, it is necessary to ensure consistent ground coverage separates signal and power planes.

Copper Features 

As important as the location in the stack of the power and ground planes is the physical shape of the copper features. Form follows function, and performance requires ample surface area to avoid the creation of locations of high heat and surface current density in excess of what the copper is able to withstand. Avoid excessive neckdowns, and be mindful of designing around board shapes or features with irregular extents that can further inhibit performance.

Power Shapes

As a general reminder, current in the plane will follow the path of least impedance, meaning loops will want to take the most direct route from the supply or power circuit to an ICs respective power pin. A plane design that captures all of the necessary pins may still be liable to performance issues if the path for the current is more heavily localized towards one side or edge of the shape. To that end, avoid excessive concavity when designing power shapes, which can serve to trap current and heat. A better solution, if available, is to design the power shape across multiple power plane layers. Doing so requires overlap at areas of high via concentration (typically the source of the power) to avoid a situation where a small number of vias are responsible for providing the current flux necessary for a power plane shape.


Power integrity may even extend into the realm of materials. High-current designs may require a thicker copper-clad laminate to provide the requisite thermal and electrical characteristics that accompany a greater surface charge density. Doing so may restrict routing by reducing the possible trace thickness producible from acid etching.

Graphic showing the difference between a 90o angle and a 45o angle in design

The addition of an intermediate 45o edge in the bottom design helps improve the path for the current to flow. Note that the lines are simple representatives of the current path; in actuality, current flows throughout the plane based on the path of least impedance.

Power integrity is a high-level topic that demands some understanding of the underlying physics and engineering solutions that can alleviate the design; luckily, Cadence’s toolset of PCB design and analysis software handles the computational heavy-lifting, leaving designers to do what they do best. Get started with OrCAD PCB Designer to see how our powerful, yet easy-to-use design environment contains all the necessary features for today’s PCB needs.

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