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Power Integrity Fundamentals in PCB Layout

Key Takeaways

  • The importance of power integrity in circuit board design.

  • The fundamentals of power integrity.

  • PCB design tips to avoid power integrity problems.

Circuit board

I like to think of power in a circuit board as a vast lake of clear, serene water that abundantly supplies the needs of a PCB. You could sail a little boat across this lake without a care in the world because the lake is so calm and inviting. For years, PCB layout engineers approached power and ground with this kind of thinking—as long as a board had VCC and ground planes, an endless supply of power was available for the taking by simply dropping a via into it. However, with today’s high-speed designs, the truth is quite different.

Instead of a calm and picturesque lake, the supply of power in a circuit board can be a stormy nightmare filled with ripples and waves threatening to swamp a little boat. The components necessary for high-speed circuits demand a lot of power, creating spikes that threaten the smooth operation of other parts on the board. For the best performance of a circuit board, the integrity of these waters must be managed so that the board has an even and continual supply of power for all of its needs. Here are some power integrity fundamentals that can help you calm the storms of the power delivery network in your design.

Circuit Board Problems Due to Flawed Power Integrity

At one time, circuit board components were simple enough that many only had one power and one ground pin on them. These devices were really easy to work with, especially the thru-hole versions, as they easily connected to the VCC and ground planes of the board. Even their bypass capacitors were simple to place and route, as they nestled right on top of the part where they could easily be routed to pin 14 of the IC. Additionally, these parts were not as sensitive to minor fluctuations in the power delivery network, and their signal speeds were not fast enough to create problems either. But, with the components used in high-speed designs today, this has all changed dramatically.

The power delivery networks (PDNs) of circuit boards have to be carefully managed to provide clean power across the PCB to all of its components. A board that hasn’t been designed for good power integrity can exhibit a lot of problems, such as power ripples that create crosstalk in the high-speed circuits of the board. We’ll look further at the different types of problems bad power integrity can create for circuit boards, but first, let’s look at the results of these problems:

  • Excessive noise in a PDN will affect the voltage levels required by components, and if they drop below the acceptable level, the associated circuits may malfunction.
  • Even if the voltages are within the tolerance required by the part, the noise on the PDN may appear as crosstalk on signals, causing those signals to be misinterpreted.
  • PDN noise has the potential of radiating EMI through the planes and connections of the power delivery network.
  • All of the above can create a huge headache for designers during test and debugging.

Obviously, good power integrity in PCB design is essential to the success of the design, so, let's explore some power integrity fundamentals.

 Components placed and routed in a circuit board design

These components are laid out to facilitate short and direct routing, which helps with power integrity

Notable Power Integrity Fundamentals

Good power integrity in a circuit board means that its power delivery network is designed to provide stable voltage references and to distribute power to all of the board components within acceptable noise and tolerance levels. The PDN has to be able to distribute power evenly throughout the system—from the power supply to associated routing and vias, through the planes and capacitors, and finally into individual devices. Each device on the board needs strictly controlled and consistent voltages supplied to it for consistent and stable operation. Some of these devices, such as large pin-count processors, require several different voltages and higher amperage than other parts to run. The demands of these components have to be managed by the PDN or they will adversely affect other components on the board. Here are some of the specific power integrity problems designers need to consider when they design PDNs.

Ground Bounce

With the increased switching rates in high-speed designs, the low state of a signal may not return all the way back to the reference ground level. This ground bounce is also known as simultaneous switching noise or SSN. As the low state of the signal drifts upwards, it may eventually be misinterpreted as a high state, leading to false data being transmitted.

Power Ripples

The switching of an SMPS (switched-mode power supply) can cause power ripples to spread out through the design. These ripples could potentially create crosstalk, overwhelming and disrupting the operation of nearby circuits.

Electromagnetic Interference

The switching of an SMPS between its on and off states can create EMI if not designed correctly. Not only will EMI affect the smooth operation of the circuitry on the board, but it can also interfere with external electronics. EMI is also closely associated with how the power and ground planes of the board are configured. Not only do these planes conduct power and ground for the PDN, but they also serve as an effective shield against EMI. How the planes are configured must take shielding into consideration as well.

Signal Return Paths

Although clear signal return paths are part of creating good signal integrity, reference planes are part of the board’s PDN system and must be considered when designing for power integrity. High-density parts will have a number of vias for signals and connections to power and ground, but these vias can block the clear return paths on the reference plane. Also, some power requirements may lead designers to split a plane, as in the picture below. However, those splits may impact the clear return path of high-speed signals—creating even more EMI—and must be designed carefully.

Now that we’ve seen some basic power integrity problems, let’s look at the PCB layout best practices and power integrity fundamentals that will help prevent them.

The split planes of a circuit board design displayed in Allegro’s PCB Editor

PCB split planes

PCB Layout Tips for Good Power Integrity

When laying out a PCB design, here are some areas to pay close attention to in order to avoid some of the power integrity issues that we’ve been discussing.

Board Layer Stackup Configuration

The PDN of a board is closely tied to the configuration of the layers in the board stackup. Ground layers must be strategically placed to provide microstrip and stripline layer configurations for sensitive signal routing. These layers will provide the clear signal return paths needed, as well as provide EMI shielding. It is also important to lay out the plane layers to ensure that all of the power is delivered to each part. This may require splitting the power layers for different voltages. By developing a floorplan of the design first, you will have a better idea of the different functional partitions, and configure your PDN accordingly.

Component Placement

Reference voltages must be carefully managed in your PDN to ensure that the components receive the power they need. This will prevent ground bounce from causing false triggering of sensitive signals. Doing this means adding multiple bypass capacitors to stabilize the PDN from the demands of processors and other parts that consume a lot of power. You will want to place these capacitors as close as possible to the power pins they are tied to. Placing parts close together like this on the same side of the board is also important for power supplies, where short and direct routing is essential. Remember to keep analog, digital, and power sections of circuitry isolated from each other to prevent power supply noise from interfering with analog and digital signals.

Trace Routing

When routing from power pins to bypass capacitors, keep the traces as short as possible. When routing power supplies, keep those traces as short, wide, and direct as possible using 45 degree or rounded corners. Wider traces are necessary for the increased current and temperature of power nets, and, at the same time, will reduce inductance on the line and help prevent crosstalk. Shorter routing in the PDN will also minimize the potential for these traces to behave as antennas and create additional noise. Remember to keep digital and analog routing away from power supply areas to protect them from that noise.


It is always best to use a solid plane for grounding instead of routing ground with traces. This will help with thermal management and power integrity, but it will also help with signal integrity by providing clear signal return paths for sensitive high-speed transmission lines. Remember, though, to not block the clear signal paths with cutouts, splits, or large groups of vias. When you create a ground plane, make sure that its outline encompasses all of the components to help with EMI shielding. And, above all, remember to carefully plan plane splits to ensure that power is distributed evenly to all parts.

There are a lot of features in PCB design tools that can help with creating good power integrity on designs, and we will look at how to best utilize these features next.

Allegro’s Constraint Manager highlighting some of the design rules that can be made

The Constraint Manager used in Cadence’s Allegro PCB Editor

Better Power Integrity Through PCB Design Tools

Today, PCB design tools typically have many features and capabilities that will help with power integrity fundamentals in your design. For instance, Cadence provides many different tools and resources for developing your board's PDN and creating good power integrity. The IR Drop Analysis featured in this video is one example of that. The Allegro PCB Editor has a lot of functionality built into it to help as well.

In the picture above, you can see an example of the Constraint Manager built into the Cadence tools. With its spreadsheet-style interface, the Constraint Manager allows you to specify component classes, net classes, spacing rules, and trace widths. By setting up the specific values you need for power components and nets, you can control part spacing and trace widths while you are working, instead of having to retrofit them later. Additionally, Allegro has multiple trace routing and copper pour features, allowing you to precisely connect the PDN according to your design’s needs.

For more information on creating a PDN for your design, take a look at this E-book.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.