Issue link: https://resources.pcb.cadence.com/i/1532922
critical length to know what a 'safe' outer layer trace length should be. For instance, if your signals are pushing 40 Gbps (20 GHz Nyquist) and quadruple the MT/s of USB 3.2 then cut 1500 mils down to a quarter of what we put for USB 3.2. (i.e. 1500 mils / 4 = 375 mils). But that's a rule of thumb. Verify with TopXplorer. The real-world requirements can vary significantly depending on dielectric and conductive materials of the PCB, coating, environment, etc. If you do need to use a rule of thumb and don't have access to simulation, then a very conservative value is 1/20th the signal wavelength. Verify with simulation later. 4. Finally, go to Electrical > Net > Routing > Wiring. 5. Click and apply the appropriate ECSet onto the desired net by selecting the ECSet from the Referenced Electrical CSet column. The rule is automatically applied to that net. Notice how the CLOCK signal adheres to the Exposed Length restriction (green color means it adheres/is good), with margin to spare (12.089 mm to work with). As an experiment, adjust the margin to something like 1 mil and see what happens to the same row being analyzed. It will turn red immediately, since the Constraint Manager is always active. Key Note: For the rest of this project application, follow the instructions from previous parts of the guide as the steps are the same. We will show images of our implementation for this design. 45 www.cadence.com OrCAD X Constraint Management Guide