Issue link: https://resources.pcb.cadence.com/i/1532922
Reminder: Stub Length Limits are used to ensure tight signal integrity and minimal reflections and antennas, namely for nets that carry signals with extremely short rise times (30 picoseconds or less, 5 GHz or higher frequencies). Similar to stub length limits, we need to limit total trace length on the outer layers of the PCB to avoid EMI that are picked up by or transmitted from said traces. Maximum Exposed Length Set a maximum length for exposed stubs to prevent unintentional antenna effects. This is particularly important for high-fre- quency signals where wavelengths are shorter. A general rule of thumb is to keep stub lengths below 1/20th of the signal's wavelength, but please note that each situation depends on simulating the conditions for your specific stack-up, your dielectric and conductor materials, signals being transmitted and preliminary signal integrity analysis. Rules of thumb, while can often be a good enough solution sooner, can still lead to re-spun boards later without proper simulation. TIP: You can perform signal integrity analysis and simulations pre-layout, during layout and post-layout using TopXplorer. To ensure that you're on track with your signal integrity goals, use information on signals propagating through your design and are using IBIS models for your transmitting ICs and simulate them in TopXplorer. For example, this differential pair, CLOCK (CLOCK+ and CLOCK-) from the images in the Stub Length section of this part can be analyzed as it is right now. You want to simulate the circuit topology, test some conditions to find out what will make it compliant with your Stub Length requirements. To do such analyses on any net, right click the Net Class/Group/Diff Pair object name, select Explore Topology. IMPORTANT NOTE: If you get an error message regarding licenses not being available, you first need to download and install the correct version of Cadence Sigrity X Aurora software (for example if using OrCAD X 24.1, then install Sigrity 24.1 and its subsequent updates for that base version 24). After that, even when installed, you may need to create and set the Environment variable (SIGRITY_EDA_DIR = C:\Cadence\ Sigrity2024.1) in both the local and system environment variables in Windows. Finally, open LMTools (would be installed from the License Manager software from Cadence) from the Windows Start menu. Then go to the Start/Stop/Reread tab, click the ReRead License File button, then after waiting for 10-20 seconds, click the Stop Server button, then wait another 5-10 seconds, then click Start Server. After another 5-20 seconds (the LMTOOLS by Flexera window might stop responding during this time, but it will respond eventually), you can run TopXplorer from the Constraint Manager. 42 www.cadence.com OrCAD X Constraint Management Guide