Issue link: https://resources.pcb.cadence.com/i/1532922
The routing adheres to this layer set rule (at least for CLOCK+ and CLOCK-) but does give some indication/warning about the lengths of trace material that were ignored in the process. Strictly speaking, it is not realistic for no amount of trace to fall outside a layer restriction. So, some is acceptable/ignored. To visualize this, here is the CLOCK+ signal trace shown below. Now that this is finished, let's move to Vias. Maximum via count Set the maximum number of vias for a trace or net to maintain impedance control and minimize parasitic capacitance. Each via introduces discontinuities and can degrade signal integrity, especially at high frequencies. The maximum number of vias we will allow on traces that take on the DIFF Constraint set is 4 Vias (ideally it should be 2-3, but 4 can work in our case). Here is the Constraint set being modified: 48 www.cadence.com OrCAD X Constraint Management Guide