Issue link: https://resources.pcb.cadence.com/i/1532922
We see the routing is within range for our signal integrity related constraints we made in the Electrical Constraint Set named DIFF. Relative signal velocity Understand and account for the relative speed at which signals travel through different PCB materials and trace geometries. This knowledge is crucial for accurate timing calculations and can help prevent board re-spins due to signal integrity issues. 52 www.cadence.com OrCAD X Constraint Management Guide