Issue link: https://resources.pcb.cadence.com/i/1532922
Propagation delay modeling Create accurate models of signal propagation delays to account for potential signal degradation during operation. This helps with timing analysis and ensuring proper synchronization in high-speed designs. We set the Constraint Set values to the ones shown below (All Drivers/All Receivers at a Maximum Delay of 500 picoseconds = 0.5 nanoseconds). Then when we check our design (which takes pin delay into consideration) we see that we're within our constraints (we are still within the DIFF Constraint ECSet, as a reminder). Total etch length limits Set maximum trace lengths to avoid critical timing issues and signal degradation. This is particularly important for high-speed signals where longer traces can lead to increased attenuation and skew. Let's say our total etch must not exceed 85 mm based on calculations from the materials, dissipation factor of the dielectric, conductive material type, etc. That rule gets applied to the Constraint Set under Maximum Total Etch, as shown below. Then we check if we're within spec, it shows that we are well within range. 50 www.cadence.com OrCAD X Constraint Management Guide