Issue link: https://resources.pcb.cadence.com/i/1532922
We will stop there for now, but know that you can do all sorts of things like different analysis types and options, frequency response and even S-parameter extraction. The findings from such analysis methods can be back-propagated as desirable constraints back into the Constraint Manager. Then the PCB designer can use those new constraints as the rule of law to finish laying out the PCB to meet requirements. Results-driven design (i.e. from simulation findings and requirements) is a mandatory part of the process to support first-time right design and fewer design iterations and re-spins. TopXplorer is a signal integrity tool that adheres to the results driven design standard for modern PCB designers and hardware engineers. Let us switch gears back to maximum exposed length. In the next set of steps, we will show how to set the maximum exposed length of conductive material that is allowed on the outer layers of the PCB (top and/or bottom). Steps on how to change maximum exposed length outside the PCB: 1. Similar to the stub length rule application, open the Constraint Manager. 2. Create an electrical CSet in the Electrical Constraint Set > Routing > Wiring worksheet OR use an existing CSET (e.g. DIFF). 3. Set the Max Exposed Length to say, 750 mils (17.780 mm). Design Note: This value was chosen arbitrarily as half the 1500 mil critical trace length for a USB 3.2 differential pair signal operating at 5 GHz Nyquist frequency (i.e. 10 Gbps) from a Texas Instruments controller from their datasheet recommenda- tions. The reason being that the rise time for that chip and a 10 Gbps per second signal hovers typically around 20-30 picoseconds and the speed of travel to avoid reflection is around the 1500 mil mark. Then, we decide to cut that in half to be more on the cautious side, since we want at most, both outer top layer and outer bottom layer traces to result in that 1500 mil limit. However, you must verify with the chip manufacturer and/or designers the expected signal speed and acceptable 4 4 www.cadence.com OrCAD X Constraint Management Guide