Issue link: https://resources.pcb.cadence.com/i/1532922
Notice that our region-based constraint set is applied to the Regions worksheet in a specific BGA region instead of being applied to various nets. Note: There are spacing regions for the DDR2 and DDR3 devices, but we have not created spacing constraints for either of these devices since they're using SOIC packaging instead of BGA packaging. Upon inspecting the pin sizes for the SOIC packaging, we don't need to adjust the default spacing or physical settings for our traces. Electrical Properties Within the Constraint Manager, we can assign properties and values to specific nets. This feature is extremely useful for doing PCB layout simulations (e.g. power IR drop analysis, signal integrity transmission line simulation). See the image below to find the electrical properties section. Notice that in the Properties > Net > Electrical Properties worksheet, you can set so many parameters: f Frequency (the rate of pulses per second on a net. Also, the inverse of the Period) f Period (the time between when a signal repeats itself. e.g. the time from the beginning of one pulse to the beginning of the next pulse) f Duty Cycle (the length of time a pulse on the net will be high within the signal period) f Jitter (the amount of jitter expected on the trace for that net) f Bit Pattern (this is the signal pulses that are expected on a net, such as 01011001) 22 www.cadence.com OrCAD X Constraint Management Guide