As they say, “everything changes except the schedule.” As designers, we know that and we keep our heads down and plow through the last 100 connections before the due-date. We were smart and kept the design rule violations to a minimum. We shared our work with nightly back-ups. Those continually shared designs were embellished with an email that summarized the tasks and pointed out any risks every single day.
Image Credit: Author - A little light at the end of the tunnel might be an oncoming train of improvements. Leaving work for the last day might wind up being the reason for a schedule slip.
Signal and power integrity rules were baked right into the constraints so that the design was compliant from start to finish. Simulation and iteration of the virtual board has satisfied the experts that the board will do its thing. The learning curve was flattened as much as possible by design reuse of known good circuits. The noisy power supplies and those emo receive chains couldn’t be farther apart. We did everything they asked and more.
All of the reference designators for the silkscreen and assembly drawings were organized for the placement review some time back. All that is left are the incidental text overlaps that resulted from massaging the placement for better routing. Oh, and of course, there were a handful of new parts to splice in with each schematic revision. No doubt, you imported the netlist one more time just to make sure nobody was trying to pull a fast one over on you.
Preliminary files were shared with the fab and assembly units and, of course, the vendors had their comments on how you can make it easier for them. Like a good designer should, you plugged all of that information into the database. The stack-up and the controlled impedance line geometry are pre-approved from the fabricator. There will be no surprises on that end.
The assembly sub-panel has all of the right features for the pick & place machine to align the components over the footprints. In addition to the tooling holes and fiducials, the break-off area has metal thieving to thwart any warpage concerns. The panel accounts for all of the edge connectors. There’s even an arrow on the panel to show them which way the board will travel through the reflow oven.
Image Credit: Author - Part of the endgame includes generation of the assembly sub-panel. Whether it is created by you or the CAM team at the PCB factory, it has to account for the limitations of the assembly equipment.
Fiber weave effect on the transmission lines has been accounted for. Anyone trying to point out a location for another via along those stripline and microstrip traces obviously didn’t look at the layers above or below the traces. Any more vias around the antenna area will starve the board of dielectric necessary to maintain the impedance. We have to leave something for the power planes and traces.
Isolation between the critical lines is only compromised where the components simply will not allow a guardband. Even then, it’s all balanced out to share the pain evenly. The memory busses are tuned to spec and look nice and airy while still being compact. The high speed pairs are absolutely elegant! Even the untrained eyes can spot the clock nets by the oversized air-gaps.
You spaced the high voltage section with consideration for the conductive anodic filament growth. The thermal path from the junction of the die all the way to Mother Earth is rock solid. Temperature rise and voltage drop will be manageable. The ring of ground around the perimeter of every layer keeps your noise in and their noise out. No static at all; the strong grounding keeps ESD events off of the inner sanctum of the board.
The dimensions are complete and jibe with everything the product design handed over. There are no parts in the keep-outs and all of the limited headroom areas are accommodated. The library symbols have been double checked against the data sheets. There is no doubt about pin-one on every IC, unmistakable polarity marks on the tantalum caps, cathode pins of the diodes are clearly shown with everything repeated from the assembly to the silkscreen.
Part numbers and revision levels match the drawings. The design notes are complete and coherent. Environmental and emission regulations are covered. The soldermask is the right color. You did your job. All of the little details were squared up when the check-plots came out for "final'' review. So, the end-game should be a low-stress victory lap. Why is that never the case?
This is the nature of our work. When Leonardo da Vinci started painting the Mona Lisa, it was a blank canvass. No critic could say, “Put a little smile on her lips but make her eyes say, What are you looking at?” This is not to say that our PCB artwork is on any level with one of the greatest minds of the Renaissance or that it would ever be seen in the Louvre. Just that they can’t comment on what they don’t see.
Image Credit: Leonardo Da Vinci (by way of Wiki)
Until we connect all of the dots, it’s difficult for anyone to bless the placement. Personally, I know I wind up moving things around to make way for a via or some other routing element during fan-out and routing. We try our best to put the components in their respective locations and then find out where we were wrong.. Even when the space is sufficient for the routing plan, that only means that the placement could probably be tightened up here and there.
PCB design is a dynamic process. We never start out with the complete story. Working through the uncertainty is a risk/reward process. Once all of the details are known, the board may be somewhat calcified but it’s a lot closer to done than the blank canvass where it all started. A Designer who takes pride in doing the work but is practical enough to accept unforeseen circumstances will go far.