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How to Suppress NFPs in OrCAD

PCB mounting holes

Whether for purposes of signal integrity or reliability, the removal of non-functional pads (NFPs) comes up as a question again and again. Typically, if you do not know how to remove NFPs, but it is recommended they be removed, they can be deleted manually from a design using CAM software. Not all CAM operators or PCB fabrication companies will apply these modifications, so it might be up to the designer to make these changes in their PCB layout data.

If you’re an OrCAD user and you want to see how to quickly make these modifications, there are several options you can access inside the PCB layout. This way, you won’t have to go back to PCB libraries to make these changes, and they can be applied only to a specific design.

Why Remove NFPs From a PCB Layout?

When NFPs are included in a PCB layout, the NFPs can create advantages and disadvantages in two areas: reliability and signal integrity. Because they anchor to internal layers, they can affect reliability in thick PCBs with through-hole designs. At high speed/high frequency, the NFPs act as a location for capacitive coupling to a grounded pour that reduces impedance. Choosing to remove NFPs is about balancing these two aspects of a design.

The pros and cons of using and removing NFPs from vias and pins are outlined in the table below. This table focuses on the two primary areas of reliability and signal integrity.




  • Can anchor internal sections of a via or pad that resist expansion
  • Higher quality plating along drill holes as there are more seed points
  • Provides channels for CAF growth in internal layers
  • Each internal NFP creates another drill hit that wears down drills

Signal Integrity

  • Can be used to tune impedance of via transitions in broad bandwidths
  • NFPs will not have noticeable effects below about 10 Gbps data rates
  • Additional capacitance could reduce impedance of via transitions
  • Can create dips in insertion loss spectrum (corresponds to high return loss)

If a designer is unsure as to whether to keep or remove NFPs from a board, consider these rules of thumb:

  • If reliability is more important, especially in thermal cycles, keep the NFPs
  • If cost is most important, the NFPs can be removed
  • If signal integrity is most important, the removal should be verified in simulation and measurement
  • NFPs will not have noticeable SI effects at low frequencies, so they can often be kept in the design

By default, padstacks will include the NFPs on internal layers unless the designer specifies they must be removed in their CAD software. If you do decide to remove NFPs along vias or through-hole pins, OrCAD offers several options to modify padstacks and remove NFPs without modifying component libraries.

How to Remove NFPs on Pads and Vias in OrCAD

NFPs can appear on both vias and through-hole pads, and the procedure to modify these differs depending on whether the instance is a pad or via. There is also a way to remove all instances of NFPs by modifying the artwork export settings. The three approaches are as follows:

  • Purge NFPs from groups of through-hole pin and via padstacks
  • Manually remove NFPs from selected vias and pads
  • Swap with a padstack that does not contain NFPs
  • Suppress all NFPs from specific layers in the output artwork

OrCAD PCB Editor contains multiple options for removing NFPs, depending on whether you want to swap with a new padstack, modify an existing padstack, or suppress pads on artwork.

Suppress NFPs From Groups of Through-Hole Pads

As an example, take a look at the through-hole pad arrays on these power nets. These plated holes are connected to terminals with moderate voltage output and a ground net. While the voltage is not high enough to produce arcing, the voltage and spacing to the internal pour are such that, over time, there might be dendritic growth (CAF) given the potential for excess moisture to become trapped in the PCB layers. The same argument around NFP removal from through-hole pads applies to vias that might be connected to high-voltage nets.

To help reduce this growth, NFPs can be suppressed on a group of pins or vias by using the Purge feature. First, locate the pins where you want to remove NFPs.

Remove NFPs OrCAD

Through-hole pin arrays with NFPs.

To remove NFPs from a group of pads or vias, select the Tools/Padstack option in the main menu, then select Modify design padstack. This will bring up a panel where the existing padstacks in the design can be browsed and selected. If you know the name of the padstack that applies to your selected pins/holes, you can select it and use the Purge function to remove the NFPs.

Remove NFPs OrCAD

If you are not sure which padstack belongs to your selected pins, just click on one of the pins, and its name will populate in the Name field in the Options panel.

If you are unsure of how to use the Purge function or if you have other modifications that need to be made to the pins/vias, you can right click on the selected instances and select the Edit option.

This option will open the Padstack Editor. In this window, navigate to the Options tab to configure NFP suppression. In this tab, you will see an option for “Suppress unconnected internal pads” in the window. Toggle this option to set the presence of NFPs. When the padstack has been edited, select File/Update to design so that the padstack updates in the layout. This is required to ensure the update to the padstack appears in the PCB layout. Note that this will not update the padstack in your library, it will only update the instance used in the PCB layout.

Remove NFPs OrCAD padstack editor

Removal From Selected Via and Pin Padstacks

Another way to suppress NFPs without opening the padstack list in the Options panel is to select individual pins and vias, and then modify the padstack for that pin/via. This can be applied to an individual pin/via, or it can be applied to the padstack and will be applied to all pins/vias with that padstack.

As an example, take a look at the vias connected to the gate drive ICs in the image below. Some of these vias are closer together, and depending on the voltages involved you might want to remove the NFPs to provide maximum spacing.

 Remove NFPs OrCAD

To remove NFPs from specific vias, select the vias you want to modify, right-click, and select the Modify design padstack option. To just modify a selected via, choose Single instance to change one via. To modify all vias with matching that padstack, select All instances.

The same process applies when using the All instances selection under Modify design padstack. If there is a different padstack in the design that already has the NFPs suppressed in the padstack design, you can use the Replace padstack option when you right-click on the selected via.

Replace Padstack or Modify Library Entry

Within the above pad modification workflows, you will also see an option to Modify library padstack or Replace. The Replace option allows you to select a padstack that already exists in the library, so if there is a duplicate padstack without NFPs it can be quickly applied with this option.

The other option for modifying the library entry directly is not recommended for NFP removal unless it can be confirmed that this will not affect any other designs using that library. Instead, just modify the current instances requiring NFP removal, or create a duplicate padstack without NFPs and use the Replace option.

Removal From Artwork

NFPs can also be removed from the artwork exports when creating the PCB fabrication files for your projects. This option will override the design settings in your padstack, and the options can be applied to copper layers as a group.

To access the artwork settings for your PCB fabrication file exports, open the Export menu and select the Gerber option. This will open the Artwork Control Form window as shown below. Inside this window on the Film Control tab, there is a “Suppress unconnected pads” option. Select this option to remove NFPs on the film exports. This needs to be applied to each layer individually.

Remove NFPs OrCAD

The exported Gerbers will now have all NFPs on internal layers removed automatically, and the CAM operator at your fabrication facility will not need to manually modify the fabrication data to remove these pads. This will not modify the pad-to-pour clearances that were already present in the PCB layout, so you will see the expected large hole-to-copper clearances in the exported artwork.

A typical workflow in these kinds of designs is to keep most NFPs in the PCB layout, and then apply suppression in the film export settings if it is later determined that NFPs should be removed. This gives designers the ability to work quickly with various padstacks in the PCB layout, but later a designer will have flexibility to quickly delete the NFPs as needed.

Anytime you need a quick way to modify your PCB fabrication data by removing NFPs, don’t resort to CAM systems to make changes to your data. Take full control of your designs with the complete set of CAD tools in OrCAD from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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