In our last post, we covered differential signaling, a key routing architecture found in high-speed PCB designs that uses two voltage signals that are equal in magnitude and opposite in polarity to create a single high-speed information signal.
Differential pairs are popular in high-speed designs because they give you faster data rates with increased protection from EMI and crosstalk. But your ability to enjoy these benefits hinges on one important design rule: the lengths of the traces in a differential pair must be equal.
In this post, we’ll cover the best practices behind trace lengths and how OrCAD’s Total Etch Length feature makes length matching easier.
What happens when the trace lengths of a differential pair are unequal?
You might think that this could lead to a timing issue, given the way a differential pair carries a data signal. In reality, many differential circuits can still switch reliably with significant timing differences between the two signals in a differential pair.
The real reason you want to keep your differential pair trace lengths equal has to do with preserving the architecture’s natural resistance to common mode noise.
When differential signals are equal and opposite, their return currents cancel out. High-speed signals will still induce a coupled signal to an adjacent trace or plane. But as long as the lengths of the traces in a differential pair are equal, the induced noise remains contained within a closed loop. This gives you a lot of flexibility in your design (e.g. the sender and receiver can have different ground potentials).
Problems occur when your differential pair signals are no longer equal and opposite. When one trace is longer than the other, an impedance mismatch is created, and your return currents no longer perfectly cancel out. Uncontrolled ground current can lead to the common-mode EMI problems and noise that you were trying to avoid in the first place when you used a differential pair.
Constraint-Driven Design Flow with the Total Etch Length Tool
So you’re convinced it’s in your best interest to keep the trace lengths equal across all your differential pairs, what’s the best way to ensure you don’t slip up as you try to route all the traces on your board?
One way might be to adopt a constraint-driven design flow by making use of the Total Etch Length feature in Cadence’s Constraint Manager. This tool makes it easy to assign minimum and maximum etch length values to differential pairs, nets, buses, or Xnets.
Constraint violation markers can draw your attention to problem areas in your design while seamless integration with Cadence Allegro allows you to analyze your signals from the Constraint Manager in real-time—all as you route your differential pairs.
Ready to adopt a constraint-driven design flow in your PCB workflow? Check out Cadence’s suite of PCB design and analysis tools today.