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LVDS Signals Crashcourse

Key Takeaways

  • LVDS is a widely used standard for high-speed, low-power, and low-noise differential signaling. It is employed in applications such as high-speed video, graphics, data transfers, and computer buses.

  • LVDS operates with a low voltage swing, ranging from 250 mV to 450 mV, allowing for faster rise and fall times and higher operating frequencies than other technologies.

  • LVDS offers advantages such as low power consumption, minimal noise coupling, low EMI emissions, and superior switching capability

LVDS signals, also known as TIA/EIA-644, is a widely used standard for high-speed, low-power, and low-noise differential signaling. LVDS signals are used in applications for high-speed video, graphics, data transfers from video cameras, and general-purpose computer buses.  Its advantages include low power consumption, minimal noise coupling, low EMI emissions, and superior switching capability compared to other standards. Furthermore, LVDS is highly reliable and efficient in transmitting high-speed digital signals while maintaining signal integrity. Read on as we discuss LVDS signals, their function, and important aspects of their voltage levels and swing.

As shown here, a basic LVDS circuit signal can consist of a differential amplifier with output nodes VOUT connected to a receiver in parallel with a low-valued resistor.

LVDS signals, also known as TIA/EIA-644, is a widely used standard for high-speed, low-power, and low-noise differential signaling. LVDS signals are used in applications for high-speed video, graphics, data transfers from video cameras, and general-purpose computer buses.

 Its advantages include low power consumption, minimal noise coupling, low EMI emissions, and superior switching capability compared to other standards. Furthermore, LVDS is highly reliable and efficient in transmitting high-speed digital signals while maintaining signal integrity. Read on as we discuss LVDS signals, their function, and important aspects of their voltage levels and swing. 

Typical LVDS Implementation Voltage Level

Value

Voltage Level (V)

Power VDD

+2.4~3.3V

Input High Threshold (VTH)

VCMO + 100mV

Common Mode Offset VCMO

1.2 V

Input Low Threshold (VTL)

VCMO - 100mV

Ground VSS

0V

Input thresholds are the minimum differential voltage (positive or negative) on the receiver inputs that result in either a high or low logic on the receiver’s output.

LVDS Signal Architecture and Function

LVDS employs differential signaling, where information is transmitted as the voltage difference between a pair of wires, compared at the receiver. The transmitter supplies a constant current, typically of 3.5 mA, with its direction determining the digital logic level. This current passes through a termination resistor (usually around 100-120 ohms) matched to the cable's impedance, resulting in a voltage difference of approximately 350 mV.

This low differential voltage of about 350 mV is another noteworthy characteristic of the LVDS signal. This low voltage level contributes to LVDS's power efficiency, as it consumes significantly less power than other signaling technologies. For instance, at a 2.5 V supply voltage, driving 3.5 mA of current results in a power consumption of approximately 8.75 mW. In contrast, an RS-422 signal would dissipate approximately 90 mW in the load resistor. For this reason, LVDS's low power consumption makes it an attractive choice for energy-conscious applications.

 By tightly coupling the wires, LVDS minimizes electromagnetic noise generation by canceling electromagnetic fields created by opposite current flows. Additionally, the tight coupling reduces susceptibility to common-mode noise interference, as any noise affects both wires equally, but the differential voltage sensed by the LVDS receiver remains unaffected.

LVDS Voltage Levels

One of the key aspects of LVDS is its voltage levels, which play a crucial role in its performance and compatibility with various integrated circuits. In typical LVDS implementations, the common-mode voltage, which represents the average voltage on the two wires, is around 1.2 V. This low common-mode voltage allows LVDS to be used with a wide range of integrated circuits that operate at power supply voltages as low as 2.5 V or even lower.

One such example is sub-LVDS, introduced by Nokia in 2004, which operates at a typical common-mode voltage of 0.9 V. Another variation is Scalable Low Voltage Signaling for 400 mV (SLVS-400), which enables LVDS operation with power supplies as low as 800 mV, with a common-mode voltage of approximately 400 mV. These variations cater to specific requirements and provide further versatility in LVDS applications.

Additional LVDS Variations

Multipoint LVDS, is another extension of the original LVDS standard and addresses the need to drive multiple receivers using a single transmitter in a multipoint topology. To fulfill this demand, Bus LVDS (BLVDS) was developed as the first variation of LVDS specifically designed for driving multiple LVDS receivers. BLVDS enables the efficient transmission of digital signals to multiple recipients, expanding the possibilities and applications of LVDS technology.

LVDS Voltage

Common-Mode Voltage

Description

Typical LVDS

~1.2 V

LVDS used with ICs down to 2.5 V and lower power supply voltages.

Sub-LVDS

~0.9 V

Introduced by Nokia in 2004, operates at a common-mode voltage of approximately 0.9 V.

SLVS-400

~400 mV

Enables LVDS operation with power supplies as low as 800 mV, common-mode voltage ~400 mV.

Additional LVDS Variations

Multipoint LVDS

Extension for driving multiple receivers with a single transmitter in a multipoint topology.

Bus LVDS (BLVDS)

Designed for driving multiple LVDS receivers efficiently.

LVDS Voltage Swing

One of the key factors contributing to the LVDS signal’s effectiveness is the unique, relatively smaller voltage swing.

Specifically, LVDS utilizes a low-voltage swing approach, leveraging a differential constant current source scheme. This scheme allows LVDS to achieve maximum data rates of up to 655 Mbps, with theoretical values reaching up to 1.923 Gbps. Using a typical current of 3.5 mA, the standard LVDS setup features a voltage swing from 250 mV at a minimum to 450 mV at a maximum, with a typical value of 350 mV.

The relatively low voltage swing of LVDS brings several advantages to the table. Firstly, it requires less time to rise and fall, enabling higher operating frequencies than traditional CMOS and TTL technologies with identical slew rates.

Unlike single-ended systems referencing the signal to ground, LVDS's differential transmission scheme rejects common-mode noise, providing a robust and reliable data transmission solution.

In designing circuits involving LVDS signals, it is crucial that system designers can ensure optimal performance by following good design practices. This includes routing the differential signals in close proximity through controlled impedance traces or cables, minimizing the potential for noise interference.

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