Understanding How to Reduce Impedance in PCB Design

July 2, 2024

Cadence PCB Solutions

Key Takeaways

Understand the importance of impedance in PCB design and how it affects signal propagation and power transfer.
Learn techniques like using low-impedance components, optimizing trace lengths, and employing ground planes to reduce impedance.
Utilize SPICE simulations, AC frequency sweeps, transient analysis, and harmonic balance analysis for accurate impedance measurements.

Do you know how this inductor will affect the impedance of a circuit?

Impedance affects how signals propagate through the board, how power is transferred between components, and how signals bleed into unwanted areas of your PCB. There are a number of analyses you can use to determine or reduce unwanted impedance in a circuit, but these do not always produce realistic results unless you include the right parasitic elements in your models.

Tips On How to Reduce Impedance

Category	Tips
Component Selection	Use components with low impedance characteristics at the operating frequency.
PCB Layout Optimization	Shorten trace lengths to reduce inductive reactance. Increase trace width to lower resistance and inductance. Use ground planes to reduce loop inductance and provide a return path for signals. Avoid right-angle turns; use 45-degree angles or rounded corners.
Controlled Impedance Techniques	Use differential pair routing; keep pairs close and matched in length. Employ impedance matching networks (resistors, capacitors, inductors) to minimize reflections.
Power Delivery Network (PDN)	Use multiple decoupling capacitors close to power pins to reduce high-frequency impedance. Optimize power and ground planes to ensure low impedance paths between power sources and loads. Ensure the spatial distribution of impedance in the ground plane minimizes loop inductance and EMI susceptibility. Signals will follow the path of least reactance back to the ground return when traveling in the ground plane. Ideally, the path of least reactance in a star, point-to-point, or multipoint topology should lie directly beneath conductors in your board. This will ensure your circuits have minimized loop inductance and will have the least susceptibility to EMI.
PCB Substrate and Stackup Design	Use low-Dk materials to reduce parasitic capacitance and maintain consistent impedance. Design the layer stackup strategically to place ground and power planes effectively.
Via Impedance Reduction	Minimize via usage, especially in high-speed signal paths. Use blind/buried vias to reduce inductance compared to through-hole vias.
Simulation and Analysis	Use SPICE simulations like AC frequency sweep to visualize impedance across frequencies. Use transient analysis to identify impedance-related issues in time-domain simulations. Use harmonic balance analysis to analyze how harmonics affect impedance in nonlinear circuits. Measure impedance with impedance meters and analyzers for accurate results in the finished product.

Understanding Impedance in SPICE Simulations

Besides manual calculation, you can use the Gauss-Jordan method in SPICE simulators, which will give you the total impedance of the circuit and the respective components. In the time domain, the arrangement of circuit elements will affect the transition to steady-state behavior, which can be analyzed with transient analysis or pole-zero analysis.

Impedance calculations become complex with nonlinear components like diodes, transistors, and amplifiers. The impedance, defined by trans-impedance at a specific input signal strength, varies as the input signal changes, affecting both individual elements and the circuit's overall impedance.

Using SPICE Simulation Tools for Minimizing Impedance

AC Frequency Sweep: Visualize impedance across frequencies.
Transient Analysis: Identify impedance-related issues in time-domain simulations.
Harmonic Balance Analysis: Analyze how harmonics affect impedance in nonlinear circuits.

Optimizing PCB Layout to Minimize Impedance

In a real PCB layout, impedance can differ significantly from the schematic's ideal due to substrate and trace arrangements, leading to effects like crosstalk. High-frequency switching can cause power integrity issues like ringing. The power delivery network's impedance also deviates from ideal capacitive behavior at higher frequencies, affecting signal and power integrity.

Transmission Line Impedance

The impedance of a transmission line is normally 50 Ohms, although it may take a different value depending on the signaling standard used in your device. As an example, LVDS specifies that the differential impedance of a differential pair should be 85 Ohms.

Reducing Impedance in Transmission Lines

Differential Pair Routing: Keep differential pairs close and matched in length.
Impedance Matching: Use matching networks (resistors, capacitors, inductors) to match the impedance of the source and load, minimizing reflections and impedance discontinuities.

Transmission line impedance also depends on the arrangement of nearby lines. Parasitic capacitance from the PCB substrate and mutual inductance between lines result in even and odd mode impedance, accounting for their coupling and driving mode (common or differential). Common and differential impedance are related, bringing the total number of impedance values to five.

Blue traces in a PCB layout

These traces may act like transmission lines if they are long enough.

Proper Trace Design To Reduce Impedance

Shorten Trace Lengths: Keep signal paths as short as possible to reduce inductive reactance.
Increase Trace Width: Wider traces have lower resistance and inductance.
Use Ground Planes: Ground planes help reduce loop inductance and provide a return path for signals, minimizing impedance.
Avoid Right-Angle Turns: Use 45-degree angles or rounded corners to reduce impedance discontinuities.

Power Delivery Network Impedance

Your power delivery network (PDN) shows capacitive impedance at low frequencies and reduces the resistance of the power bus, load components, and ground path at DC. This impedance is influenced by the physical separation of power rails, traces, and internal planes. At higher frequencies, mutual inductance increases PDN impedance, resulting in peaks. Ideally, PDN impedance should be flat within the working frequency band. For digital signals, this band spans from the clock rate to the knee frequency (0.35 divided by the signal rise time). Analog signals also benefit from a flat transfer function across the board and ground planes.

Minimizing Impedance in Power Delivery

Use Multiple Decoupling Capacitors: Place capacitors close to power pins to reduce high-frequency impedance.
Optimize Power and Ground Planes: Ensure low impedance paths between power sources and loads.
The spatial distribution of impedance in your ground plane is also important, particularly in mixed-signal devices. Signals will follow the path of least reactance back to the ground return when traveling in the ground plane. Ideally, the path of least reactance in a star, point-to-point, or multipoint topology should lie directly beneath conductors in your board. This will ensure your circuits have minimized loop inductance and will have the least susceptibility to EMI.

Impedance spectrum of a power delivery network

Example power delivery network impedance spectrum

PCB Substrate Material Selection and Stackup Design

Due to the parasitic effects mentioned earlier, you will need to carefully select a substrate material and design your stackup. The dielectric constant of your substrate will affect the geometry required to produce a transmission line with specific impedance and will affect the impedance of the power delivery network. The presence of planes beneath conductors also determines the loop impedance in a circuit, which affects a circuit’s EMI susceptibility.

How to Reduce Impedance Through Substrate Selection

Use Low-Dk Materials: They reduce parasitic capacitance and help maintain consistent impedance.
Stackup Design: Optimize layer stackup to ensure ground and power planes are strategically placed to minimize impedance.

Via Impedance

Just like a PCB substrate will have some parasitics between neighboring conductive elements, so will vias in a multilayer board. The inductance of a via is on the order of nanohenries and depends primarily on its aspect ratio. Vias also have self-capacitance, and groups of vias have some mutual capacitance and mutual inductance. This leads to noise coupling between vias and causes vias to act as impedance discontinuities when placed on a transmission line. In general, the use of vias is generally kept to a minimum in high-speed and high-frequency circuits.

How to Reduce Impedance Through Via Usage

Minimize Via Usage: Use as few vias as possible, especially in high-speed signal paths.
Use Blind/Buried Vias: These can reduce inductance compared to through-hole vias.

How to Reduce Impedance With OrCAD X Tools

Feature	Description
HDI (High-Density Interconnect)	HDI technology compatibility in OrCAD X allows the use of blind, buried, and micro vias to maintain compact designs. By enabling efficient via placement, HDI helps reduce impedance discontinuities caused by traditional through-hole vias, which can disrupt signal integrity.
Constraint Manager	The Constraint Manager in OrCAD X provides a comprehensive environment to set up detailed rules for via stacking, spacing, and routing. These constraints ensure consistent impedance across different layers and nets, helping to prevent impedance mismatches and signal reflections.
Constraint-Driven Routing	OrCAD X offers constraint-driven routing with real-time feedback, which ensures that impedance-related constraints are adhered to during the routing process. This minimizes the risk of design rule violations and helps maintain consistent impedance, crucial for signal integrity.
Design for Manufacturing (DFM)	OrCAD X includes advanced DFM checks that cover via and trace placement among other factors. These checks ensure that the design is manufacturable while adhering to impedance standards, thus preventing issues related to impedance variations that can occur during the manufacturing process.
Shape Management	The Shape Management feature in OrCAD X allows for dynamic adjustments of copper shapes and planes. This capability helps maintain proper spacing and minimize impedance variations that can arise due to design changes, ensuring consistent signal performance throughout the PCB.
Impedance Analysis	Integrated impedance analysis workflows in OrCAD X enable PCB designers to identify and resolve real signal integrity problems. The tool provides a color-coded scale to highlight traces with high impedance and allows for adjustments to fix discontinuities, ensuring optimal signal integrity.
Cadence PCB Impedance Calculator	The Cadence PCB Impedance Calculator in OrCAD X offers multiple methods to calculate and manage impedance. It includes tools like the cross-section editor and Constraint Manager to specify and adjust impedance values, helping designers ensure that their traces meet the desired impedance.
PSpice	PSpice works seamlessly with OrCAD X to analyze impedance through various types of sweeps (e.g., AC sweep, DC sweep). This simulation tool provides detailed insights into circuit behavior, allowing designers to predict and mitigate impedance-related issues before physical prototyping.

Now that you know how to reduce impedance in your PCB designs, try out these OrCAD X tools today for free. Sign up for a free trial now!

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