ESD Protection Design for Integrated Circuits in CMOS Technology

If you are a fan of the NFL and NOT a Patriots fan, then you can relate to this next statement. Tom Brady (TB12) is the single most disruptive cause of playoff and Superbowl dreams to be crushed, dismantled, and destroyed.

This is equally true of the other (G.O.A.T.) who once dominated the NBA, Mr. Michael Jeffrey Jordan. To this day, players like the great Karl Malone, undoubtedly still has nightmares about the championships that got away due to his Airness’s greatness.

If electronic components could dream, then they would also be prone to nightmares and those nightmares would be about electrostatic discharge (ESD). According to the ESD Association, 25% of all electronics that are ‘damaged for unknown reasons’ can be attributed to ESD. These damages cost the electronics industry an estimated $5 billion a year. So, the need for ESD protection and design considerations at every level cannot be overstated.

What is ESD and What Causes the Phenomenon?

ESD is a released electrical charge (static electricity) that is at rest. This is mainly created by an imbalance of electrons that stay on a specific surface, or in the environmental air. The imbalance of electrons, caused by an absence of or a surplus of electrons, causes an electrical field that is capable of influencing other objects at a distance.

ESD also refers to what occurs when two objects with opposing charges come into contact with one another. If these two objects get close enough the voltage is discharged, creates a voltage spike, and generates an electromagnetic field.

We experience the effects of ESD on a fairly regular basis. Studies have found that a typical human body can build up charges (called “electrostatic potential”) of between 500 and 2,500 volts during a single 8-hour workday. However, damage to an electronic component can occur at around 25 volts.

The Importance of ESD Protection

ESD failure is one of the most challenging reliability problems to integrated circuits (ICs) and other electronic systems. In fact, industrial statistics suggest that more than 30% of IC failures are caused by ESD or electro overstress (EOS) events, resulting in billions of dollars in losses annually to the industry.

However, knowing that there is a problem and realizing the solution to the problem are not mutually exclusive. Furthermore, the current solutions in place are not a one-size-fits-all solution. Although these EMIs (electromagnetic interferences) may indeed pose an equal level of danger to electronic systems, their methods of attack are not uniform.

Knowing what you can do to prevent EOS events saves time and money

It is universally acknowledged that ESD protection is required for all ICs and other electronic products. However, not every precaution is equally effective for every ESD model encountered. I will elaborate further over the next few paragraphs, the different models and protection issues they pose. This will also further illustrate as I eluded to earlier, that a one size fits all approach is not warranted.

Types of ESD Stress Models

ESD may occur in various situations. In order to better address these concerns, these ESD stress models have been separated into three specific types or models. The three types of ESD stress models are the Human body model (HBM), machine model (MM), and the charged device model (CDM).

These three elementary models are used in the industry to measure the ESD protection level of ICs and to evaluate the impact of ESD stress in different situations.

Human Body Model

HBM, as its name implies, represents ESD stress caused by the ESD phenomenon that occurs when an electrostatically charged human body contacts a chip and forms a discharge path. 

Machine Model

MM represents ESD stress caused by the phenomenon that occurs when a charged machine or tool with a static charge contacts the chip and forms a discharge path to the ground while on the production line.

Charged Device Model

The CDM is a scenario where the IC (integrated chip) is charged during fabrication, production or transportation. Furthermore, the charge transfer takes place between the inside and the outside of the IC after the IC comes into contact with any conductors or ground.

ESD Protection Design in CMOS Technology

Electrostatic discharge (ESD) protection design is needed for integrated circuits in CMOS technology. The choice for ESD protection devices in CMOS technology includes diodes, MOSFETs, and silicon controlled rectifiers (SCR).

However, these ESD protection devices come with some unwanted side effects. Simply put, they cause signal losses at high-frequency input/output (I/O) pads due to the parasitic capacitance. Therefore, to minimize the impacts of these ESD protection circuits on high-frequency performance, ESD protection circuits at I/O pads must be carefully designed.

Once you are able to reduce parasitic capacitance, ESD protection circuits can be easily combined or co-designed with high-frequency circuits. As the operating frequencies of high-frequency circuits increase, on-chip ESD protection designs for high-frequency applications will continuously be an important design factor.

CDM ESD Protection Design Challenges

Over recent years, with the extensive use of automated machinery and equipment on production lines, CDM has proven to be the most destructive discharge mechanism of all ESD stress models. CDM has gradually become the most important concern in terms of ESD protection design.

Creating an ESD safe environment will help increase reliability in testing 

One of the most important characteristics of CDM is the low impedance discharge path, which leads to an extremely rapid charge transfer. This particular attribute is what makes CDM such a concern in the design consideration for ESD protection in CMOS technology. Here’s why, during the CDM discharge, the rise time is very short (typically, 0.25-0.75ns), which requires short trigger times of CDM ESD protection designs.

In addition, with the improvement of chip integration technology and the development of new packaging techniques, the equivalent parasitic capacitance of the chip increases. Thus, resulting in an increase in the amount of charge carried by the chip and this requires an increase in the protection capability of CDM ESD protection designs.

In conclusion, the importance of ESD protection design for ICs in CMOS technology cannot be overstated. With the ever-increasing evolution and capabilities of ICs in terms of application and functionality, it is clear that designs for ESD protection must evolve as well.

Cadence’s suite of design and analysis tools, will have designers and production teams working together towards the best ESD protection design for integrated circuits and any CMOS technology. Allegro PCB Designer is the layout solution you’ve been looking for and it can surely facilitate the best ESD protection design for all of your integrated circuit needs. 

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.