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CAN Bus Hardware Design Offers Practical Software Solutions

Key Takeaways

  • CAN bus hardware offers many attractive features, especially in today’s global market.

  • Safety features need to be supported by a strong signal integrity underpinning. 

  • No clock here: CAN bus topology and signal transmission on a two-wire setup.

Internal simplified connections of a CAN bus system

CAN bus hardware enables the communication between sensors distributed throughout a car

After a little experience laying out boards, most designers become intimately familiar with communication protocols and the extra care involved in routing them. Most often, this means length matching of critical lines like clocks, data differential signals, and other signals that require a tight timing tolerance for the circuit to perform as intended. PCB development and programming are closer to the century-mark than their inception, and several communication protocols have established themselves, some much more ubiquitously than others. 

A controller area network, or CAN bus, is one that ranks below the upper echelon of well-established protocols that have entered common parlance, but it is by no means uncommon. From vehicles to building features, CAN bus hardware design features prominently in many industries where safety is paramount. In doing so, the CAN bus has offered a solution to overly-cramped boards and amplified software solutions that used to be confined to on-chip programming.

CAN Bus Hardware Design

In the simplest terms, a CAN bus marries disparate elements of system circuitry to achieve a more comprehensive response to environmental and user stimuli. The expanding use of standby data from sensors has seen great development in recent years in automation subsets such as machine learning. In some ways, the interconnectivity between sensors in CAN bus topology represents something of an early predecessor. Initially designed in the automotive space, its usage has expanded into additional transportation industries such as agricultural equipment, aviation, maritime, and business functions. By facilitating communication between these subsystems, some noteworthy advantages emerge:

  1. Cost reduction - By using extant circuitry, systems avoid having to add in additional sensors or components to cover functionality that already has the necessary tools present. Fewer components mean fewer chances for defects that lead to rework or scrap during the wide array of assembly processes. Moreover, with the current global chip shortage, any design process that can reduce the overall component count is almost a necessity.
  2. Improved layout - More components contribute to a reduction in usable board area due to the land patterns as well as routing on external and internal layers. An increase in design density demands more time spent on layout, and, taken to its extreme end, the potential for a complete revision or expansion of the board dimensions for proper distribution.
  3. Software implementation - Using in-design components reduces a hardware solution into software, which has the additional effect of being more flexible during testing and debugging. While there are constraints to working within the framework of on-board components, software solutions have greater adaptability that may lend themselves to functionality in excess of what hardware alone could offer.

The benefits of CAN bus hardware design is a double-whammy of efficiency, reducing cost on the front-end while giving developers a range of software implementations on the back. 

Signal Integrity Underlines Safety

Many safety features that have gained prominence within the past decade (some of them becoming mandatory by new standards) arose from the communication offered by CAN bus communication. The most basic feature, yet revolutionary in terms of safety, is brake by wire, which is an electronic override of the brake pedal to bring the vehicle to a stop. Combined with proximity sensors in the front of the car or on the side-view mirrors, the system now has a method to accelerate the vehicle to a stop to avoid collision (and liability) on the part of the driver. Therefore, signal coherence is critical when discussing a network comprised of safety features. Even small changes in travel time could result in samples being misaligned, and in a fast-moving vehicle, this could resolve fatally. 

PCB Substrate and Signal Integrity

With this knowledge, designers must additionally emphasize signal integrity best practices. One outsized area of impact on the signal integrity is the substrate used to build the PCB. Depending on the loss tangent, the signal is more or less likely to attenuate as it moves through the medium. The glass fiber weave of the PCB substrate, which provides rigidity and form to the board, can also contribute to the loss effect. Length-matched signals need to arrive at the same time at their destination in order to avoid timing mismatches, but the assumption that the substrate has a uniform loss tangent is more often than not incorrect. A loose weave can have the signal pass over gaps between the fibers, which possess a larger loss factor. 

For low-speed signals and short traces, the travel time is unlikely to be significantly affected by the substrate underneath. However, higher speed signals and longer traces mean two or more signals have a greater chance of an unsynchronized arrival. To address a flaw inherent to the media, manufacturers not only provide substrates with alternate materials with reduced loss but also tighter weaves. A tighter weave either minimizes or relatively eliminates the gap between orthogonal threads, creating an environment where a signal loss in any direction or orientation is negligible.

Oscilloscope performing eye diagram

An eye diagram of an MLT-3 exhibiting strong signal integrity

Dominance and Recessiveness of Asynchronous Communication

Designers are used to clock signals driving communication protocols, but CAN bus functions asynchronously. CAN operates under a bitwise arbitration setup with a dominant and recessive bit methodology. Through the lens of circuit analysis and logic states, the dominant “0” logic state occurs when CANH (one of the two differential AND-evaluated signals) is higher than CANL. When CANH CANL, the recessive “1” logic state is output. 

Without synchronization (in terms of resolving conflicting data), there needs to be another method to settle disputes between simultaneous bitstreams–this is where the dominant/recessive status comes into play. All transmitters send and receive only recessive when recessive is the only bit present, and similarly for dominant. 

When there is a conflict between dominant and recessive bits, the dominant bit signal supersedes the recessive bit signal. In terms of translation, this results in the dominant-bit signal passing the remainder of its bits into the CAN bus while the recessive-bit signal transmission for the current 16-bit string is interrupted. It will, however, resume transmission at the beginning of the next cycle. Ultimately, this forms a ranking system where the lowest-numbered bitstream forms the highest priority message which is received and acknowledged in descending order of priority. 

For any CAN bus hardware design implementation, you want to be assured that your greater safety features are built up from the most granular elements on the board level. To start a project with best design practices at its heart and verification tools only clicks away, Cadence’s  PCB design and analysis software offers solutions to reduce complexity without sacrificing safety. 

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