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Understanding Interconnect Resistance and Transients in Simulations

Key Takeaways

  • Parasitics in interconnect circuit models for ICs and PCBs will determine transient signal behavior.

  • The two types of interconnects have different dominating factors that influence transient signal behavior.

  • The bond wire inductance at the output from an IC also needs to be considered when modeling a source signal from an integrated circuit.


Interconnect resistance in an IC

Interconnects in your PCBs and ICs share some common characteristics.


Many engineered systems exhibit mathematical and physical parallels, and these parallels become obvious if you look hard enough. This is one reason oscillators are discussed in such a non-specific way in mathematics and physics textbooks; the same concepts apply to mechanical and electrical oscillators, as well as any other type of oscillator. PCBs and ICs are linked beyond the solder that attaches them together in a board, they share some common traits at a deep physical level.

Interconnect resistance and impedance are two important concepts that govern transient signal behavior in PCBs and ICs, and these important concepts need to be considered during the interconnect design phase. Whether you’re routing on FR4 or lossy silicon, you’ll need to evaluate your device’s behavior with pre-layout simulation tools to ensure signals behave as expected. Here are the important points to include in any circuit simulation for interconnect resistance and impedance.

PCB vs. IC Interconnect Resistance and Impedance

Go back to your electronics 101 classes for a moment, and you should recall what determines interconnect resistance:

  • The conductivity of the metal that forms the interconnect;

  • The cross-sectional area of the interconnect;

  • The total length of the interconnect.


This is just the resistive portion, but there is still some reactive portion, even at high frequencies. In fact, the skin effect in the conductor provides a new resistive and reactive contribution to the interconnect impedance. These points apply to both PCB interconnects and IC interconnects. The impedance of an interconnect and its matching to a load component will determine power transfer through a system, but transient signal behavior becomes much more important in high speed/high frequency systems.

Real interconnects are more than just resistive, there is parasitic capacitance and inductance along the length of an interconnect. In examining a circuit model for IC and PCB interconnects, you need to use a standard transmission line model. The lumped element model is a powerful tool for understanding interconnect impedance and how it relates to interconnect geometry. Normally, you would cascade multiple sections in series (i.e., like a Pi filter). Alternatively, the lumped circuit model can be summarized using the per-unit-length equivalent circuit values as shown below.


Interconnect resistance simulation

Basic equivalent circuit for simulating interconnect impedance with a 50 Ohm load. Note that your simulation values will differ.


More advanced models should use a large number of lumped elements to provide more accurate transient analysis results. For real interconnects in ICs and PCBs, different portions of the equivalent circuit shown above will have dominant contributions to the interconnect impedance. This is an important point to consider as you want to focus on the critical circuit elements that will dominate signal behavior.

What Dominates Interconnect Impedance?

In PCBs, the resistance and capacitance together determine the overall interconnect impedance. This is because traces on a PCB have larger cross-sectional area than their IC counterparts, so their resistance is lower than the inductive impedance along an interconnect. Once signal bandwidths get into the 10’s of GHz, the skin effect starts to become important in PCB transmission lines, and the impedance will start increasing beyond the standard saturation value.

Within an integrated circuit, there is a larger contribution from the interconnect resistance, simply because the conductor cross-sectional area is smaller. This outweighs the shorter trace lengths used in integrated circuits. But what about the inductance? The inductance and capacitance still combine to produce an interconnect impedance that is quite small compared to buffer stages in an IC.

So why should the interconnect resistance matter? The important point here is the RC delay created by the interconnect resistance and parasitic capacitance in an IC, both of which are much larger than the corresponding values in a PCB. A driving transistor has some output capacitance that should be included in a circuit simulation. The combined RC delay created by the output capacitance and interconnect resistance slows the signal rise time. As transistors have scaled smaller, the capacitance has quadratically scaled larger, causing delays along interconnects to increase at smaller technology nodes (see below).


RC interconnect resistance and delay in integrated circuits.

Calculated gate delay and RC interconnect delay trends at different technology nodes in ICs.


Pre-layout simulations do a good job of accounting for signal behavior in the presence of the equivalent circuit elements shown above, but they still fall short in two areas: dispersion and skin effect losses. Pre-layout simulation in the form of transient analysis, though, is particularly valuable for circuit analysis by examining the phase and magnitude of the current of a circuit or providing voltage drop measurements for specific components within the circuit. 

Other important parasitics, such as bond wire inductance, also need to be considered during the design phase as these contribute to propagation delay and they modify interconnect impedance. Calculating parasitics of interconnects pre-simulation, though, can shorten calculation time and speed up the design cycle with parameter extraction and providing accurate models. Accounting for these important aspects of signal behavior requires a 3D field solver or more advanced analytical techniques.

Real Interconnects Need 3D Field Solvers

Pre-layout simulation features cannot account for interconnect resistance and impedance modifications via the skin effect, nor can they properly account for dispersion in the dielectric substrate. You can get a good idea of transient signal behavior with a time-domain pre-layout simulation, but taking your design to the next level requires post-layout simulations with a 3D electromagnetic field solver

With the right simulation features, you can account for dielectric dispersion, the skin effect in your conductors, and the package/board geometry directly, rather than using an equivalent circuit model. This gives you a more realistic view of signal behavior and helps you evaluate the accuracy of your equivalent circuit models.

Interconnect resistance and impedance are important ideas in PCB design and analysis, and you’ll need to use pre-layout and post-layout simulation applications to verify your designs. The front-end design features from Cadence integrate with the powerful PSpice Simulator, making them ideal for designing high speed ICs and PCBs at the circuit level and simulating signal behavior. Once a design is ready for signoff, you can use the SI/PI Analysis Point Tools for post-layout verification and simulation. You’ll have the features you need for signal chain design and optimization.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts