Your via current simulation tools can help ensure these vias don’t get too hot
Vias in a power delivery network, on a transmission line, or connecting a bypass capacitor to a ground plane will affect the behavior of the current. Although we would like to think of vias as purely resistive, this is not the case. Instead, they provide some inductive or capacitive impedance in your circuit. Here’s what you need to know about analyzing the behavior of your vias and running a via current simulation.
DC vs. AC Via Current Simulation
Just like any other conductor in a PCB, your via has some finite resistance and will dissipate some small amount of power as it carries DC current. In some devices, the vias placed between the power and ground planes in your PCB will cause some DC power to be lost as heat due to their inherent resistance.
Determining the power dropped by a power delivery network as current travels to components, which includes the power plane, traces, and vias, has an effect on the allowed AC noise margin in your components. IR drop along the power delivery network reduces the total margin, as shown in the figure below.
How via current affects the AC noise margin in your PCB.
Your noise margin will depend on the logic family used in your digital components, or on the threshold voltage in transistors that appear in AC components. For digital components, you the noise margin is generally taken as the minimum margin in the ON or OFF states (e.g., this would be ~0.5 V with most TTL families that run at 0-5 V). For analog components, you should check your datasheets for your components and set the noise margin at the lowest value among all components that will appear on your board.
The geometry of a via causes it to act like an LC when it carries AC signals, meaning an ideal via is purely reactive and average power dissipation is zero. In reality, a via’s inherent DC resistance does dissipate some heat when the via carries a switching digital signal or AC signal. Since an idealized via is purely reactive, we could theoretically run an infinite amount of AC current through the via without worrying about temperature rise. In reality, the DC resistance of a via still limits the current to some value.
In the DC case, a via should be sized such that the via current is limited to produce some acceptable voltage drop for a given temperature rise. In the AC case, you are using the same calculation, but you need to consider the RMS current carried by the via. For digital signals, you can use the current in the ON state to size your vias. In any of these three cases, your goal should be to check that the current in any of your vias does not exceed the maximum allowed current corresponding to a given temperature rise.
What You Should Analyze in a Via Current Simulation
For a single via on a power rail connected any number of components in parallel, you can easily determine the current and voltage drop across the via without simulation tools. The current will just be equal to the total current drawn by all the components. The power dissipated by the via is just the current squared, multiplied by the via’s DC resistance. One easy way to examine a via’s DC current and the power it dissipates is to use a power delivery network analyzer. This will show you the DC current and voltage drop in a via, as well as the approximate temperature of the via during operation.
For an AC or switching digital signal, it is important to understand how the inductance and capacitance of a via, any components on the interconnect, and the arrangement of these components affect the current. You can then include other components in the circuit to see how current moves through the via and how current is affected by all components in the circuit. In effect, your via current simulation is examining the behavior of an RL (at low frequencies) or RLC circuit.
For complex components, it is best to import component models into your simulation. The via itself will generally have very low DC resistance (were talking milliOhms for filled and unfilled vias), and its inductance will be on the order of nH. When building a via current simulation, the via appears as an inductor in parallel with a capacitor and resistor. The inductance and capacitance of a via with annular rings is:
Via capacitance and inductance. These values should be used in a via current simulation.
where D2 is the anti-pad diameter, D1 is the via pad diameter, and T is the via length; all dimensions are in inches. In the inductance equation, h is the via length and d is the drill hole diameter. You can now place a via in your circuit simulation as a parallel LC circuit.
To set up the via current simulation, you’ll want to ensure that power and/or signals are identified within the simulation. Then, determine and add DC paths through voltage and Thevenin sources to secure simulation parameters. Be wary of ideal sources, though, as it can skew impedances and resistances.
There are two points you should analyze in a via current simulation:
You should look at the transfer function with an AC sweep to see how different frequencies are attenuated or amplified near resonance. With digital signals, you should perform transient analysis to determine how the presence of the via affects ringing.
In any circuit with a via, you should calculate the impedance of the circuit in the presence of the via and the impedance of the via itself. This is especially important for impedance matching on transmission lines. Also, if a via connects a driver to a transmission line on an interior layer, the via’s impedance will affect component impedance matching. The same point applies to the load.
Example: Via Current Simulation on with a Bypass Capacitor
For a via in an interconnect that involves a capacitor, you will be simulating a complicated RLC circuit. Take a look at the linked article to learn more about these simulations. If there is no capacitor in the circuit, then you are looking at an RL circuit. It is important to note that, even if there is no discrete capacitor, a via on a transmission line will also be affected by the parasitic inductance and capacitance along the transmission line, which should be included alongside the component values for the via itself.
One example simulation is for a bypass capacitor connected between power and ground around a component. The bypass capacitor normally connects directly to the power pin and then connects to the ground plane through a via. In this case, the circuit you are simulating will look something like this:
Via current simulation for a bypass capacitor
Note that the current source in this circuit is meant to show that the power supply must supply the current drawn by the load. This current can be sourced as a series of digital pulses. This circuit can be easily examined for a number of initial conditions. Here we haven’t accounted for coupling between multiple vias or any other parasitics, which complicates things in a real PCB layout.
This via model is rather simplistic, and there are more advanced models out there for different via structures. If you want extreme accuracy in your simulation, then you should be sure to account for the self-resonance frequency of your bypass capacitor and any decoupling capacitors that appear on the power rail. This is critical for diagnosing ringing on the power rail. You could also consider the parasitic capacitance for any pads on the load component (appearing as a capacitor in parallel across the load).
Sizing Vias with a Calculator
If you do not have access or patience to use a via current simulation tool, there are some simple calculators you can use to calculate the size of a via for a given current carrying capacity and temperature rise. Visit this page to get access to a calculator program for sizing vias that you can run in Excel. This calculator will show you the via size you need to limit temperature at or below a certain value.
An important point regarding this calculator: it is important to note that this calculator only accounts for the DC resistance of the via in a power delivery network. If you are not in the mood to use a calculator, you can always size your vias to the specifications in the IPC 2152 guidelines.
Running a via current simulation is easy when you use the right PCB design and analysis software package. The simulation tools in OrCAD PSpice Simulator and the full suite of analysis tools from Cadence make it easy to examine power distribution throughout your PCB and determine whether current in your vias exceeds important design limitations.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.