Are you ready for terabit Ethernet? You’ll need decision feedback equalization...
When you talk to most PCB designers about digital signaling, they are used to working with two signal levels: HIGH and LOW, ON and OFF, +5 V and 0 V… any way you want to name it, you’re dealing with binary signals at standard logic levels. This works just fine for most applications on a PCB and is standard for low-speed busses as well as the single-ended portion of interfaces like DDR.
However, in advanced signaling standards like PCIe 5.0 and 50GE networking, multi-level signaling (MLS) schemes, data encoding schemes, and equalization methods are used to increase data transfer rates without increasing clock rates as well as to ensure signal recovery over physically long data links. Equalization schemes have long been used in telecom on the transmit end to ensure sufficient signal strength, but they are also implemented at the receive end to provide signal recovery at the receive side of a link.
Signals in higher-speed systems, both on the PCB and over copper or fiber, can experience significant inter-symbol interference (ISI) and jitter as well as some external noise. Among the popular equalization schemes used for high speed data links, decision feedback equalization is one popular scheme for estimating the signal level in the presence of various noise sources and accurately recovering data in the received signal. As the world tries to move to 400 Gb/s and beyond, decision feedback equalization and related schemes will be critical for working with data links that use advanced MLS schemes like PAM4.
MLS Schemes Used in High Speed Data Links
Before jumping into decision feedback equalization, it is important to understand some important aspects of MLS schemes, particularly pulse amplitude modulation (PAM) schemes, which are used in 10Base and faster Ethernet links.
The following graph shows an example that introduces the challenges involved in signal recovery in MLS schemes and other high speed digital communication channels. The blue curve shows a bitstream used in non-return to zero (NRZ) signaling, and the red curve shows a bitstream transmitted with PAM4 signaling, which is an MLS. By dividing the full output voltage range into 4 levels, PAM4 allows 2 bits to be transmitted within each unit interval (UI), effectively doubling the data rate compared to NRZ or any other 2-level signaling standard. However, the margin between each signal level is lower, making these signals easier to corrupt.
NRZ vs. PAM-4 signaling
Similar graphs can be drawn for other varieties of PAM. For example, various IEEE 802.3 standards use PAM3, PAM5, PAM16, etc., depending on the data rate and carrier frequency implemented in the design. In contrast to PAM, NRZ is a line code in a binary bitstream that never drops to 0 V; simple level shifting can be used to convert an NRZ bitstream to another bitstream without further encoding. In terms of the data carried by NRZ, it is equivalent to PAM2 and is typically slow enough that equalization is not needed.
Why Use Equalization Schemes?
The voltage difference between signal levels in PAM and other MLS schemes can be small enough that signal recovery becomes difficult. Because of the possibility of signal integrity problems like ISI, jitter, and attenuation, the difference between signal levels in an eye diagram becomes even smaller. Equalization methods are used to recover signals in the case where an eye diagram begins to close at the receiver, including with PAM signals (Ethernet or PCIe), as well as in other standards like USB 3.0 and DDR5.
The image below shows the effects of attenuation in transmission over fibers and subsequent conversion to a digital bitstream at a receiver. As we can see, PAM4 has a severely closed eye compared to NRZ or on-off keying (OOK).
Example comparing eye diagrams in NRZ or on-off keying (OOK) with PAM4 after fiber transmission over various distances
The above comparison of eye diagrams should illustrate how the presence of noise at the board level and the transceiver level becomes problematic in PAM and other MLS schemes. For a given maximum signal level (e.g., 5 V), the noise margin for each signal level starts to become comparable to the difference between signal levels as more levels are added. While a 0.5 V noise margin may be fine with standard TTL/CMOS logic, this is unacceptable when working with MLS schemes like PAM4. Add to this jitter/skew and the noise floor in the system, and your system is at risk of higher BER than the same system operating with NRZ. In general, MLS schemes will run at lower SNR than the same system operating with NRZ or any other 2-level digital bitstream. Equalization is used to overcome these noise problems.
Equalization in Advanced Signaling Standards
Equalization schemes have been used to provide jitter/noise immunity to digital signals running at high data rates on FR4 when interconnects span beyond the recommended maximum length. A recent example was examined with USB 3.0, where a simple equalization scheme was used with standard NRZ inverted (NRZI) signaling. NRZI signaling was found to be robust against jitter and did not require complex adaptive equalization schemes to ensure signal integrity. More advanced standards will use different equalization schemes to pre-emphasize signals at the transmitter or to recover signals at the receiver.
At this point, you have two options to ensure digital data can be accurately recovered:
Pre-emphasis equalization: This effectively passes the signal through an amplifier and filter before injecting it into a channel. The idea is to anticipate the distortion and noise effects in the channel and apply the appropriate signal modification before transmission.
Receiver equalization: The receiver can use a technique to estimate the signal level once it’s received. This can be used with pre-emphasis at the transmit side of a channel.
Example of pre-emphasis applied to a binary bitstream (normalized scale)
Decision Feedback Equalization
Equalization has many forms, but the goal in any equalization scheme is signal correction. Decision feedback equalization (DFE), continuous-time linear equalization (CTLE), and feed-forward equalization (FFE) are the dominant equalization schemes used with PAM4 in 400G Ethernet. The use of DFE is now being expanded into DDR5 and PCIe 5, and we can expect its use to continue into newer digital signaling standards.
Any signal that is transmitted through a channel (whether copper traces or a fiber optic cable) will experience some distortion due to the finite bandwidth (i.e., transfer function) of the channel. In particular, the response of the channel to the rise/fall of a digital signal (i.e., an impulse) creates transients that interfere with the signal level and may reflect from the receiver input, leading to ISI. Equalization is intended to compensate for this distortion/ISI and extract the desired signal in the presence of noise.
Implementing decision feedback equalization requires building on linear feedback equalization (IFE), which reproduces the transmitted signal after measuring the transient response and calculating its Laplace transform. The limitation of IFE is that it may result in noise gain, where the filtered noise is actually more intense than the unfiltered noise. It also only accounts for ISI between the current and previous bits. However, adding the distributed feedback equalization circuit will correct ISI between the remaining symbols. A block diagram of this scheme is shown below, where R(t) is the received signal and S(t) is the original sent signal.
Distributed feedback equalization circuit block diagram
The “taps” in the LFE and DFE are finite impulse response (FIR) filters. The output from the distributed feedback equalization circuit e(t) is equal to the circuit’s transient response to a sudden change between two voltage levels, i.e., S(t). In terms of the received signal and (M-1) previously received signals, the output is given by:
Distributed feedback equalization output
From here, we can see that S(n) can easily be determined from all other sent signals and the received signals and the tap values. In effect, adding the distributed feedback equalizer as an M-tap filter allows the tap value in each FIR in the DFE to be tuned to the correct value to provide sufficient noise and ISI removal. Note that the delay is equal to an integer multiple of the bit period, thus the delay line should be very precisely designed.
The goal in designing a distributed feedback equalizer is to set the tap values such that a reference signal that uses your desired modulation scheme can be accurately reproduced. The tap values can be determined from simulations or measurements by simply iterating through different tap values and comparing the input and output.
The goal is to minimize and differences between the reference signal and the output from the decision feedback equalization circuit. The two standard optimization methods used here are least mean square error and minimum mean square error. Taps can also be set dynamically using their own feedback circuits, known as adaptive equalization.
If you’re designing complex high speed data links that use MLS, you’ll need to include an equalization scheme. Using the right PCB design and analysis software package allows you to implement and analyze a decision feedback equalization circuit or any other equalization scheme. Allegro PCB Designer and Cadence’s full suite of analysis tools make equalization tasks and other important analyses easy.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.