MII and RMII Routing Guidelines for Ethernet

July 24, 2019 Cadence PCB Solutions

Stack of PCBs with MII and RMII routing guidelines

 

Ethernet and other networking technologies are positively wondrous, and you wouldn’t be able to read this article without them. With Ethernet-capable devices being so important in commercial, industrial, and consumer telecom applications, designers should take time to understand the basic architecture of Ethernet devices. MII and RMII routing guidelines are just one set of standards that weave the tapestry of modern telecommunications.

Ethernet-Capable Device Architecture

First things first, there are some important points to note about the overall architecture of Ethernet-capable devices and the associated routing standards. MII (media-independent interface) is the standard used to connect the MAC (media access control) block to the PHY (physical) layer for networking devices. These two portions of an overall Ethernet networking device perform different functions within the OSI (open systems interconnect) model. Each portion of the system performed the following functions:

  • PHY: An IC that converts digital data from the MAC and sends it along the physical networking interface as an analog signal. These ICs function as transceivers, thus they modulate the analog signals sent along the physical layer. When interfacing with a physical fiber link for Ethernet, the output from the PHY is sent to a fiber optic transceiver to convert modulated analog signals to an optical signal.

  • MAC: Functions as the interface between a CPU/FPGA/MCU/ASIC for data processing and communicating with the PHY chip. The MAC provides the required data processing capabilities, and it sends data to and receives data from the PHY.

 

The MII standard transfers 4 bit chunks of data between the MAC and PHY for communicating TX and RX data. The PHY requires its own clock at 2.5 MHz (10 Mbps mode) or 25 MHz (100 Mbps mode). Communication in MII is not bidirectional, thus the division of specific signals into TX and RX sets of signals. Note that the clock signal used to control the PHY is also used to trigger the MAC to send TX data to the PHY; data is sent from the MAC to the PHY on the rising edge of this pulse, allowing data to be transferred synchronously.

PHY ICs are also used in other communication protocols, such as USB, SATA, and Wireless LAN/WiFi. Some functionality can be integrated into the MAC layer, depending on the relevant applications. In Ethernet, the number of signals required for the PHY to communicate with the MAC is quite large under the MII standard, thus the RMII standard was developed to reduce the number of signals.

 

Ethernet block diagram

Block diagram showing connectivity in an Ethernet device

 

MII vs RMII for Ethernet

Each PHY controls a single physical interface, thus PCBs for devices like network switches contain many traces to provide communication between the PHY and MAC. In MII, each PHY requires 18 signals to communicate with the MAC, and only 2 of these signals can be shared among multiple PHY devices. Therefore, RMII (reduced MII) was developed as a variant of MII to cut the number of unshareable signals per PHY interface in half (down to 8 per PHY).

The RMII specification is also capable of supporting 10 Mbps and 100 Mbps data rates, and there are gigabit-capable variants. In RMII, the clock frequency used in the PHY runs continuously at 50 MHz for both 10 Mbps and 100 Mbps data rates. This doubling of the clock rate at 100 Mbps also allows the number of signals for communication between the PHY and MAC to be cut in half. In total, 9 signals are required for communication, of which up to 3 can be shared among multiple PHYs.

Note that some PHY ICs are multi-port, meaning that a single IC can connect to multiple RJ-45 connectors. However, the MII or RMII routing specification will still need to be used to connect between the MAC and PHY layers, regardless of the number of output ports from the PHY. Always follow the layout guidelines in the datasheet for the PHY device you are using in your PCB when planning your layout.

MII and RMII Routing Guidelines

All connections on a PCB in MII and RMII routing are point-to-point connections. Although MII and RMII use relatively low data rates, the limiting parameter that determines whether a trace can act as a transmission line is the signal rise/fall time. Unless your board is very large or your signal switching speed is very fast, reflections at the end of each connection can be ignored. The recommended trace impedance in MII is 50 Ohms +/- 10%.

Although the trace length between the PHY and MAC is generally short enough to ignore transmission line effects, you should pay attention to impedance when routing the signal and clock traces when the traces are electrically long. Since MII and RMII require clock signals between the PHY and MAC, best practices for routing clock signals should be used with longer traces. Generally, you should avoid the use of vias on traces carrying clock signals on board with impedance control as the trace impedance can be different between layers. However, as long as the impedance in each layer is carefully controlled to the right value, then the clock signals can certainly be routed through vias. This will prevent signal reflections on longer clock traces.

For the above reasons, all MII/RMII signal traces should be routed as short as possible on a single layer, and traces should be routed in a straight path. If you must turn a corner with a signal trace, the trace should bend by no more than 45 degrees. Clock lines should also be shielded with GND lines to prevent crosstalk through capacitive coupling, especially when longer traces are necessary.

Because the TX and RX data signals are triggered by the rising edge of the clock, communication in MII and RMII is synchronous. Thus, the data lines and the clock line between the MAC and PHY should be length matched. The allowed deviation in length matching depends on the rise/fall time for digital signals between these two elements, although it is generally recommended that any deviation be less than 10 mm as MII and RMII use TTL logic. Again, the allowed trace length mismatch depends on the rise/fall time of digital signals.

 

Gears with digital data

Keep your signals synchronized like the gears in a watch

 

The final important point in distinguishing MII and RMII routing relates to the number of signals used in each standard. Some PHY devices support either standard, thus some of the pins on the PHY will be unused if you are using RMII. Your datasheets will tell you which pins need to be pulled-down and which can be safely left open.

Different signal lines between the MAC and PHY should also include a series resistor to provide the right level of damping during switching. MII and RMII signal traces require different series resistors, and the full list of specifications for each interface is beyond the scope of this article. Thankfully, Renesas has compiled a full list of specifications for MII and RMII routing in a single-channel PHY. The required series resistors on signal traces in each standard can be found in their article.

When you’re designing your next Ethernet interface, you need the right PCB layout and design software to get the job done. Allegro PCB Designer and Cadence’s full suite of design tools are designed with the layout and verification tools you implement MII and RMII routing guidelines.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts

About the Author

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