Notes on Spacing

January 28, 2019 John Burkhert

Notes From the Board Room: On Spacing

A lot of what we do as PCB Designers is focused on the metal circuit pattern. So imagine drawing on a canvas with just a pencil and by the end completely covering it  with pencil marks. Then by using an eraser, you reveal the image that’s defined against the darker background. That is how etching copper works. The fabricator deposits a mask of the circuit pattern that is to remain and uses powerful acid to remove the metal from the exposed area. While our CAD system draws the lines and shapes as the positive elements, it is the space between that ultimately defines the circuit. After removing the unwanted copper areas, we’re left with a pattern. This pattern is responsible for connecting circuitry and providing solder points for components.

This organic process has limitations, but we incorporate them in our design rules. One limitation is that dissolving a thin space through a thick sheet of copper is problematic. The chemicals don’t eat their way straight down to the dielectric material. The aggressive etchant will tend to creep under the photoresist layer to undercut the metal, leaving a wider crown and a thin base. This is why the shape-to-line spacing rule is generally greater than the line-to-line rule.

 

line width measurement

Image credit: Nptel - Linewidth measurements can be deceiving

It’s a Trap

The PCB fabrication vendor has to dial in the right chemistry and feed rate to achieve a good product. One of the steps involves washing off the acid once it has eaten its share of copper. When our design incorporates a sharp inside bend, the chemicals in that corner do not wash out so well. The tiny amount left will continue to eat away at the copper. This unwanted exposure to the chemistry is called an acid trap. The ideal orthogonal edge doesn’t really exist in nature either, so we’re better off rounding the corners where possible. Design and process go hand-in-hand to generate the best approximation of the actual boards. You do your part in CAD and your vendor puts your artwork through a series of global micro-edits on a CAM station before it becomes an actual photo-tool.

Etch compensation is one of those edits. Let’s say you want a four mil line and four mil space. The vendor's equipment and process can’t just start with a mask of four mil wide and expect to arrive at the same size after all of the processing. They may have to widen the trace to four and a half to get the correct finished line width. This is why they are much happier if you give them a bit more air than metal for the targeted width. Of course, that improves your isolation. I’ll circle back to that in a bit.

The space around a trace is also responsible for preventing a short at DC where two metal objects can collide in super-slow-motion. The transition away from lead in PCBs has given rise to tin whiskers, also known as dendritic growth. This phenomenon is a menace to reliability in that the tin forms “icicles” over time. The on-going scientific study is helping to solve this issue using some semi-precious metals such as silver and palladium in the alloy.

 

metal migration

Image credit: Circuitnet - metal migration.


Even if we keep enough distance between conductors to prevent them from physically bridging, the electromagnetic waves that propagate along a trace will jump a gap and manifest on other conductors. The electromagnetic reaction lives in the three-dimensional space between the metal sheets and strips. The longer and closer two traces run, the greater the coupling. These EMI fields naturally go beyond the layer on which the traces are routed; sometimes well beyond. The first line of defense is to sandwich the traces between ground planes to limit broadside coupling from layer to layer.

Further, we can use guard bands around a potentially noisy conductor to isolate it from other traces that may share the same layer. Larger and/or faster voltage swings are the most problematic. Lines that regulate the switching speed of a system are known as “clocks” and they function by flipping the voltage up and down continuously. Other nets in the digital domain only change their state when the application requires them to do so meaning that they’re not as busy as the pace-setting clock signals.

You Can’t Please Everyone All The Time

It really becomes a matter of degree. In a moderately complex system, we make lots of trade-offs on spacing. It is quite often physically impossible to provide all of the isolation for all of the functions handled by the microcontroller.

Hypothetical instance: In order to protect the MIPI camera interface from interference, (because who doesn’t take pictures?) we may have to subject the GPS pairs to a little abuse from the Display Port. Now, when we finally get to the zero insertion force (ZIF) connector for the GPS antenna, those signals become the pampered pairs. And so it goes. The overlapping and conflicting requirements turn us into arbitration agents trying to do the best for the most. Nobody said this was going to be easy.

It’s an Analog World After All

Meanwhile, on the analog side, the receive chain listens really hard for any sort of signal to send to the amplification circuit. Any source of noise will be picked up and given a megaphone on the output pin of the analog device. We take the air-gap, guard-band, and reference planes to the extreme by adding a row or even two of ground stitching vias along the entire path, touching from pad to pad to pad.

One of our best tools for mitigating noise is to drive the signals at a common impedance. Impedance matching depends a great deal on the characteristics of the dielectric. The dielectric constant of the material along with the thickness of the layers will interact with the trace geometry to produce an impedance value.

When it is Time for a Change

Whenever a trace width or airgap changes, the impedance will follow. Component pins are the typical way that a trace becomes effectively wider. We also neck-down traces to escape tight areas. As the trade widens or narrows along its length, the impedance value changes. Any abrupt change in impedance (like a component or a via) will impact the signal as a reflection that bounces off of the discontinuity and returns a small amount of the signal back to the driver pin. That reflection may or may not adversely affect the signal integrity but it will certainly be part of the losses on the transmission line.

The budget for these flaws in the transmission line grows smaller as the resonant frequencies increase. In this case, the copper pours along the transmission line should be as smooth as possible. Automatic voiding often results in a more jagged ground flood. Sculpting the copper into a clean Faraday cage without points and slivers will reduce the chance of picking up spurious signals. A tidy airgap that defines the lane does more than just look good. Straight lines are inherently better at transmitting signals. When it comes to stripline and microstrip geometry, the pull-back on the routing layer is significant only in that it should be greater than the air-gap to the next layers in the z-axis by a factor of two, three, or more.

Two Electrons Meet in a Bar

A little extra or lost space can have a greater-than-anticipated effect in terms of the amount of coupling that will occur between two elements. We measure coupling in decibels. Decibels are on a logarithmic scale such that a little goes a long way when compared to the physical differences. We’re not here to discuss math but the formula works like this. Let’s say your current air-gap number is A and your coupling value is B; whatever those values might be. If you double the value of A, then you can expect your coupling factor to decrease to the square root of B. Alternately, half the space will increase the coupling by B squared. If you want more math, I’d suggest talking to Eric Bogatin.

In the end, space is what opens the process window, so more is better. In addition to the inter-symbol noise, each trace is also prone to generating a bit of heat. Taken together, too many signals in too small of an area start to generate a thermal issue. From Manufacturing to Assembly, to Test on to FCC compliance and beyond, space is the place where successful PC boards meet. Be there.

 

About the Author

John Burkhert

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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