Issue link: https://resources.pcb.cadence.com/i/1532922
The largest benefit for this constraint type at all is to minimize skew. Skew occurs when two or more signal traces are carrying signals that need to arrive at the receiver at a similar time, but they do not. Instead one signal arrives so early or late, that the information they are supposed to share (using parallel communication) gets out of sync or 'skewed', then the data becomes corrupt. If that happens often enough, you may get a blue screen of death (BSOD) on a computer, as an example of a system that is not unfamiliar with skew. Note that you can force the trace lengths within a match group to always match their lengths with the Longest Pin Pair found in that group. For example, let's say the longest trace you routed was DDR_DQ5 at 1600 mils (40.64 mm). That means any trace in that Match Group DDR_DQ0 - DDR_DQ7 must also be 1600 mils (40.64 mm) with some tolerance (but not too much). So the longer we make the longest trace, the longer we must make the other traces to match it. Otherwise, the signals would have skew. Match by Longest Driver/Receiver This is similar to matching by longest pin pair, but the pins just need to be a driver from an IC and a receiver from an IC. Match Length to All Driver/All Receivers This applies the rules to all traces at the same time, but you must specify a target net for the other nets to try and match their lengths with. To do that, go back to the Constraint Manager. Go to the Electrical > Net > Routing > Relative Propagation Delay worksheet. Then right click the Delta:Tolerance column for one of the nets (e.g. for DDR_DQ2). Then choose Set as Target. 54 www.cadence.com OrCAD X Constraint Management Guide