Issue link: https://resources.pcb.cadence.com/i/1532922
Note: The Max Stitch Via Distance is a rule that defines the distance at which a return path via should be present from a via of the scoped signal (see image below). 18. Apply these rules into your constraint set DDR3, then apply the constraint set to your nets by opening the Electrical > Net > Routing > Wiring worksheet. 19. Now let's apply the Electrical Constraint Set (ECSet) DDR3 to the nets DDR_DQ0 through DDR_DQ7. Click, drag, and highlight those nets. Right click on any of the highlighted net row names, then Create - Net Group. Select the net name, then Click Ok. 19 www.cadence.com OrCAD X Constraint Management Guide