Issue link: https://resources.pcb.cadence.com/i/1532922
Now the DDR3 signals will not be allowed onto the layers INNER1 or INNER2. You may change these layer sets at any time. 17. Let's add more constraints to this DDR3 ECSet, like Vias – Max Via Count = 2, Impedance, Propagation delays, Total Etch Length, Differential Pair parameters, Relative propagation delay and Return Path. Please see the images below for those values in the constraint set. Max Via Count Impedance Min/Max Propagation Delays 16 www.cadence.com OrCAD X Constraint Management Guide