Issue link: https://resources.pcb.cadence.com/i/1532922
Layer restrictions Control EMI by limiting the layers through which a trace can be routed. For example, keep high-speed signals on internal layers sandwiched between ground planes for better shielding. In our design, we want the CLOCK+ and CLOCK- signals to not be routed on the PCB surface. It is sensitive to noise and controls the timing for important devices in the design. So, we set the allowed routed layers to the internal layers (as seen below). 47 www.cadence.com OrCAD X Constraint Management Guide