Issue link: https://resources.pcb.cadence.com/i/1532922
Standard Spacing Constraints Then we have spacing necessary to maintain signal integrity for cross talk, and avoid manufacturing defects in general. Under the Spacing Constraint Set > All Layers worksheet: f Line To… f Thru Pin To… f SMD Pin To… f Test Pin To… f Thru Via To… f BB Via To… f Microvia To… f Test Via To… f Bond Finger To… f Hole To… f Min BB Via Gap Then there is the Net Class-Class > All Layers worksheet which contains the same constraints as above but allows you to set constraints between Net Classes instead of only single nets one by one. Standard Same Net Spacing Constraints For the most part, Same Net Spacing can be left as is, unless you need to change the thermal relief on the layer. But even then, that can be changed in your design properties. TIP: If you end up having shorting errors between traces and planes, then this constraints area might be the culprit. You'll want to adjust your Shape to… spacing setting such that shapes have some distance away from all other objects for isolation purposes. For example, let's say you wanted all power planes and shapes (members of the POWER_GROUP) at least ~7.87 mils (0.2 mm) away from copper pads, even if the through-hole or surface mount pad is part of the same net (you may want to do this to provide thermal relief spacing). You would go to the Spacing > Net > All Layers worksheet, then in the POWER_GROUP(10) cell, right click the cell, choose Change all design unit attributes… 30 www.cadence.com OrCAD X Constraint Management Guide