Issue link: https://resources.pcb.cadence.com/i/1532922
10. In the second row, let's consider traces that are closer together 4.2 mils (0.10668 mm). Those traces should not be allowed to run in parallel with each other as long as traces are 5 mils apart, because the coupling will be stronger from the smaller gap. Therefore, reduce the parallel length to 750 mils (19.050 mm). Please use the settings in the image below. 11. Our last constraint is Layer Sets. Maybe we want to limit the DDR3 traces to only the top and bottom layers of the PCB for example (or TOP and INNER1 or BOTTOM and INNER2) to manage EMC and board capacitance. Click the Layer Sets cell, the Select Layer Sets window appears. 12. Click Define Layer Sets… The Define Layer Sets window appears. Then click Create. 13. Now name the layer set. For example, choose 'LS1'. 14 www.cadence.com OrCAD X Constraint Management Guide