Issue link: https://resources.pcb.cadence.com/i/1532922
Schematic Constraints Overview In the modern hardware design process, constraint management must follow the design requirements, goals, features, and expectations for the product. The constraints fallout from the signal integrity, power integrity, electrical, mechanical and electromagnetic requirements necessary for the product to be considered a success. Notice on the schematic capture side, our Constraint Manager has some options for signal integrity requirements (such as signal reflections, edge distortions, etc.), crosstalk (Xtalk) performance, allowed simultaneous switching noise (SSN), and so on, while on the PCB side it does not. In the modern hardware design process, the performance requirements are set at the design and schematic, not the PCB implementation phase, as that phase it is too late to think about signal integrity and performance. In the following sections we create and apply as many of the rules (constraints) needed for the design to meet said require- ments. The main performance categories that we can constrain are electrical (e.g. impedance), physical (copper features like trace width), and spacing (e.g. distance from other objects to avoid EMC issues). After that we will want to set some net properties as well. These steps are all to facilitate the efficient execution of PCB layout for the PCB designer. Counterintuitively, the more rules and restrictions we have, the easier it is to create and route a printed circuit board. So, let's start with electrical constraints. Electrical Constraints In OrCAD X Capture let's set the electrical constraints to meet design needs. Notice the Signal Integrity and Timing sections. 1. Skip these sections and go to the Electrical - Routing – Wiring worksheet. 2. Right click on the Dsn named DEMOJ – Create - Electrical CSet… 3. Give your constraint set a descriptive name like 'DDR3', then click OK. The Constraint Manager lets you assign multiple electrical rules like the routing style, stubs lengths, parallel traces and layer sets. Set the following values as shown in the image below. 4. Once the DDR3 constraint set is created, click the cell under the Verify Schedule column and set it to Yes. This ensures that the constraints are checked during the routing process, which helps maintain signal integrity. 5. Set the Schedule to Daisy-chain. This routing pattern reduces the chances of signal reflections in the DDR3 topology by ensuring the signal terminates at the last DDR3 chip in the memory bank. 12 www.cadence.com OrCAD X Constraint Management Guide