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Choose Tx and Rx Pins Wisely on High Speed Interfaces

FPGA interfaces

FPGAs give designers plenty of freedom to instantiate custom logic and place interfaces into different I/O banks. The same applies to ASIC designers, who have some freedom to arrange internal circuits and thus place the Tx and Rx portions of an interface. Be careful when you do this, as there can be crosstalk between these lines that can ruin the link performance. However, if you end up with adjacent Tx and Rx interfaces in your packaging, then there is a simple routing strategy that will minimize coupling and ensure the interface will function correctly.

The Problem With Adjacent Tx and Rx

Given the drive to produce small packages where possible, it is tempting to place Rx and Tx lines in a link such that they are next to each other on the same edge of the package. This placement is done such that only one side of the package is needed to communicate with some peripheral component. This might also occur in components with SPI interfaces, where the MOSI and MISO lines might be put next to each other to keep the interface compact.

The package drawing below shows what happens when this is done on a custom ASIC or on an FPGA. Placing the lines next to each other allows crosstalk to occur between the lines. In high-speed serial interfaces, which are often differential pairs, the Rx transmission from the peripheral typically travels a long distance and the Rx signal can be quite weak. Differential NEXT from the Tx side of the interface has a high potential to interfere with the Rx signal and it could exceed the noise margin when the signals have fast edge rate.

 FPGA interfaces

NEXT will be induced in the Rx side whenever the Tx side drives a signal into the Tx differential pair. In a full duplex connection, which includes just about every high-speed serial differential connection, the NEXT can be coincident with an incoming Rx signal, thus leading to the interference between these sides of the interface.

The above shows an LQFP package, but the same problem would arise on a BGA package. It can also happen with fast single-ended lines coming into/out of the package on quad packages, leadless quad packages (QFNs), or BGAs. Typically these fast interfaces on a BGA would be coming from the outer rows/columns of leads on the BGA.

Stuck With Adjacent Tx and Rx?

If you are forced in a position where Rx and Tx interfaces must be placed next to each other, then there is a simple solution where traces can be routed on multiple layers. Keep the Tx copper on the top side of the board (microstrip), and route the Rx on the inner side of the board (stripline). If the additional dielectric loss in stripline configuration will run over the loss budget for the link, then swap this: put the Rx side in microstrip and Tx in stripline.

FPGA interfaces

It might be tempting to put both Tx and Rx in stripline configuration on inner signal layers, even if they are not the same signal layer. This would require routing both Tx and Rx through vias to reach the inner layers. This will increase the coupling length for NEXT, which would arise as via-to-via crosstalk. Therefore, consider keeping these on the top layer.

Is This Common on Other Components?

The problem being referenced above is most likely to be confronted when selecting interfaces for an FPGA or when designing custom ASIC packaging. The simplest way to overcome the problem is to arrange Tx and Rx pins such that there is at least one ground pin between Tx and Rx, as shown in the example below.

FPGA interfaces

In many other components, whether they are packaged in quad packaging or in BGAs, this placement of a ground pin between the Tx and Rx sides of the interface is common. This is done for two reasons:

  • It forces the Tx and Rx lines to be spaced farther from each other, effectively reaching up to 2x to 3x the width of the line
  • It helps minimize the inductive current loop spanning from the I/O power rail, bypass capacitors, and GND

Both points fit within the core concepts of ensuring stable signals being sourced onto a trace and minimizing crosstalk on low-level rails. The other key point to follow here is the use of the ground pin; it should not be used to route a guard rail between the two traces. Just ground the pin, and use a ground plane on the next layer. This will be required for impedance control and it will provide natural shielding between the Tx and Rx signals.

Electronics design teams are becoming more multi-disciplined and will need to take the lead on packaging and PCB design in complex systems. No matter what you need to design, you can build it with the best set of PCB design features in Allegro PCB Designer from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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