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Which Chip Packages Are Used in Different Applications?

chip packages

Advanced packaging design and fabrication techniques enable many new designs with heterogeneously integrated capabilities and semiconductors into a single component. Because packaging design allows so much flexibility, you tend to see different packaging styles applied in different application areas. Here is where the alignment exists between different packaging styles and cutting-edge applications.

Advanced Packaging For Advanced Systems

PCB designers and systems designers don’t necessarily have the freedom to choose what types of packaging are used to build the components they need. They will purchase a component from a distribution company or a manufacturer, and they often won’t know how the package was built. But in 2023, thanks to supply chain challenges and greater access to packaging capabilities, more companies are taking over packaging design and are building custom ASICs.

The packaging options for different types of components and some of the common areas where they are deployed are shown below.

Packaging styles and their applications. Image provided by Micron.

Each of these packages implements a particular structure that enables data transfer between dice, data transfer off-package, and provides the high I/O counts required for these parts to function. Let’s review each of these options:

AI and HPC

These two areas go hand-in-hand because AI requires so much compute to run training and inference in reasonable amounts of time. Due to the high I/O counts implemented in AI processors and accelerators, as well as the small package sizes needed when placed as accelerators, these components are typically single die components on a substrate or molded package (FOWLP and eWLB). These are BGA components typically with PCIe interface to provide fast data transfer into the chip for training and inference.

When much greater compute is needed, which would take these chips beyond embedded applications and into the data center, we see a shift to HPC structures being implemented for AI compute. INFO and EMIB structures are often used for generalized AI compute because these applications require many peripherals accessible directly inside the package. This list can include:

  • 3D stacked DRAM in-package

  • Multiple cores for parallelized compute

  • In-package power management

  • Additional low-speed interfaces and sensors

5G and Mobile Devices

Currently, the dominant packaging style used in mobile devices is the INFO packaging style. This packaging style provides the multi-die integration required to construct very small package sizes in a single component package. Handset makers prefer this style of packaging as it has enabled the thin profiles and small package sizes demanded in smartphones and similar mobile devices (smart watches, tablets, etc.).

Currently, mobile devices that require a cellular connection need an external modem to access 5G capabilities as the modem does not exist on-die. However, integration into the die may be possible if the entire chip moves to an alternative platform, but this may add expense in semiconductor fabrication. The other possibility is to integrate the modem section into a package with a standard Si die that houses the processor core.

RF Integrated Circuits (RFICs) 

RFICs could be built as monolithic components (MMICs) or as heterogeneously integrated components with multiple sub-systems. Many newer RFICs implement both a monolithic microwave die and an internal MCU that implements important processing capabilities for specialized systems.

The die for the microwave sub-system in advanced parts could have many possible peripherals built into the component, such as:

  • One or more reference oscillators

  • Fast ADCs

  • On-die memory

  • Data interfaces

  • Power management

The microwave die in a heterogeneously integrated RFIC could be built from a different material than the processing MCU die as long as both can be assembled onto the substrate with the same process. The MCU will handle data processing in these more advanced application-specific RFICs, and the results can then be off-loaded into a host processor over a standard interface, such as LVDS.

Application-Specific Packaging?

More advanced packaging modalities may still be developed going into the future, depending on what features and interfaces these components need to support. Newer components with the most advanced interfaces and technologies, such as the newest computing interfaces, may eventually drive a new approach to packaging beyond 3D integration. This is due to the instantaneous power requirements for these components, as well as the broad bandwidth requirements for the interfaces in these parts.

Electronics design teams are becoming more multi-disciplined and will need to take the lead on packaging and PCB design in complex systems. No matter what you need to design, you can build it with the best set of PCB design features in Allegro X from Cadence. Only Cadence offers a comprehensive set of IC package design and analysis tools for any application and any level of complexity.

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