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How a PCB Manufacturer Verifies Controlled Impedance

High speed pcb impedance control

High-speed PCB layouts need impedance control, which means the stackup needs to be purposefully designed to provide the required impedance target. How you get to that target requires selecting a material that enables the impedance target, but not all designers want to look through material datasheets for core/prepreg options.

Instead, you could leave that task to your manufacturer. If you’re going to do that, then make sure you understand how to specify the impedance requirement, and how the manufacturer makes sure the stackup complies with the impedance requirement.

Example Controlled Impedance Calculation

Manufacturers that need to design your stack to comply with your controlled impedance requirement will need to select the materials for the stackup. After selecting a group of materials, they can mix and match the materials until they get to your impedance target.

Here’s a simple example with a 6 layer stackup and 1 oz. copper on all layers. In the fabrication drawing, when impedance control is required, the fabrication notes might have the following items calling out impedance requirements:

  • 8 mil width/10 mil spacing on Layer 1/Layer 6 to have 100 Ohm differential impedance

  • 5 mil width on Layer 4 to have 50 Ohm impedance

In other words, the impedance has been specified based on the need for a specific differential impedance value on Layer 1, as well as on Layer 6 due to the stackup symmetry. For Layer 5, we have a secondary stackup requirement that demands a specific characteristic impedance, but no differential requirement.

How does the manufacturer get to these values? They will calculate the layer thicknesses using the dielectric constant value for the compatible materials they keep in stock. So for example, they can generate a table that shows the determined impedance value and the error from the target value.




  • 28 mil top (Dk = 4.8)
  • 5 mil below (Dk = 4.5)

8.42 mil


  • 30 mil top (Dk = 4.5)
  • 4.5 mil below (Dk = 4.2)

5.15 mil


  • 25 mil top (Dk = 4.3)
  • 5 mil below (Dk = 4.0)

6.01 mil


Based on these options, the manufacturer could select the 2nd entry in the table as that entry comes closest to the stripline impedance target for Layer 4. This would determine the dielectrics that are used between Layer 4/Layer 5, and between Layer 4/Layer 3.

If you use entry #2, then you would need to design the outer layer of the stackup for the differential signals on Layer 1 and Layer 6. The same procedure can be used to determine these materials:


Width (10 mil space)


  • 7 mil thickness (Dk = 4.6)

8.96 mil


  • 5 mil thickness (Dk = 4.3)

5.71 mil


  • 6 mil thickness (Dk = 4.5)

8.00 mil


The last entry in the table hits the impedance requirement on Layer 1/Layer 6 exactly. This will also keep the total stackup thickness at the standard value assuming 1 oz. copper. Once this calculation is completed, the designer will need to confine their routing to these layers only.

Once the board is being fabricated on the proposed stackup, the manufacturer can place a test circuit on the panel and they will then measure the impedance with a time domain reflectometer (TDR). This tool looks at the reflections along a long transmission line and uses the reflections to estimate impedance at different points along the line.

High speed pcb impedance control

Example TDR reading.

Get Stackup Data Early

If you did the smart thing and got in contact with your PCB fabrication company early, you can get their standard stackup data and you can eliminate some of the headaches involved in designing with a controlled impedance approach. If you get the stackup data, then you start out by implementing the trace width needed to reach a required impedance. If you don’t know how to figure out the width, some PCB fabrication companies can provide the trace width and spacings required for the desired impedance value.

For everyone else who wants to work directly with stackup data, some simple simulation tools can be used to determine PCB trace impedance and S-parameters without the use of an electromagnetic field solver. This kind of front-end system analysis lets a designer determine expected behavior on the desired stackup before the board is put through controlled impedance testing. You can even simulate the TDR result in the best systems analysis tools, so you will really be able to see how the signal pass from a land pattern and into an impedance controlled trace.

When you’re ready to design your high-speed PCB and simulate behavior, make sure you use the best PCB design features in OrCAD from Cadence. If you’re ready to take even more control over net logic and board layout, you can graduate to Allegro PCB Designer for a more advanced toolset and additional simulation options for systems analysis. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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