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The Frequency Response of VRMs

power VRM feedback loop

All VRMs used for high-speed digital processors are intended to provide power at high speeds, while also maintaining stable output for voltage droop and ripple. VRMs also perform important management tasks through voltage/frequency scaling, effectively modulating the output voltage to provide power savings and greater efficiency. These switching converters provide highly efficient power conversion from high input voltages, and the input voltages have been scaling higher in data center environments.

For VRM layout designers, the low core voltages involved demand proper PDN design in the PCB, as well as the right feedback loop design in circuits. Today, we can’t always assume that components used in VRMs are able to always provide stable power on their own, and there are simple layout practices a designer can implement to aid voltage compensation with a VRM circuit.

VRMs for High-Speed Processors

VRMs are a particular type of switching DC/DC converter that are designed to work directly with processors like CPUs and GPUs, although they can also work with other large processors like FPGAs. Fast devices like high-speed processors, which can have many banks of I/Os operating with fast edge rate simultaneously. These processors generally need multiple supply voltages provided on different rails, and VRMs are designed to provide these power sources to a large processor. They tend to have the following characteristics:

  • High step down (formerly 12 V to logic levels, currently 48 V to logic levels)
  • High output current
  • Fast feedback loop response time
  • Multiphase topology
  • Additional features like clock/frequency syncing, enable, temperature tracking, etc.

Among these specifications, arguably the two most important for modern VRMs are their feedback response time and topology. VRMs use a feedback loop to ensure regulation of power delivered to the load processor, and they need to respond quickly to demands for current from the processor to maintain precise regulation. They can also implement a multiphase topology to provide very quiet step-down from high voltages to low core voltage levels (as low as 0.8 V), and to provide multiple core voltage levels that are isolated from each other.

Frequency Response of VRMs

When I/Os switch, power is pulled from the I/O supply rail into the processor, which is then delivered to outputs through a buffer circuit. The ability for portions of a PDN to respond to demands for power from a processor can be seen in the PDN impedance spectrum. Normally, we omit the VRM from the impedance spectrum, but the VRM does play a role in fast power delivery particularly at low frequencies.

The frequency response of a typical VRM is shown below.

VRM impedance model

If you look at a full PDN impedance spectrum (such as in this article, see the Effects on Power Stability heading), it’s possible to identify the frequency regions where different components respond quickly due to their low impedance. In summary, we would have the following group of responses:


Response Range


Up to ~100 kHz

Bulk capacitors

10 kHz-1 MHz

Small decoupling/bypass capacitors

1 MHz-100 MHz

Plane capacitance

10 MHz-1 GHz

Package capacitance

>100 MHz

 The response ranges for these components overlap somewhat, illustrating where the inductive and capacitive regions for each group should coincide.

Modeling a VRM

VRM models that can be used to predict their frequency response can be quite complex, depending on the number of stages in a multiphase topology and the components used in these circuits. VRM models can be simple 1st-order LC models with buck/boost topology, or very complex higher-order models with multiple LC stages. These models are simple enough to solve with SPICE simulations spanning up to the MHz range.

An example VRM model is shown below. The goal in this design is to achieve a flat impedance spectrum, which will indicate a flat transient response when the VRM attempts to supply power. As the VRM’s output and control loop include reactive passives, there is the possibility for poles to arise in the transfer function, which will exhibit an underdamped transient response in a SPICE simulation. The output will be somewhat inductive, but this can be damped with capacitance on the output (see below).

VRM impedance model

48V VRM model operating at 1.8 MHz switching frequency. [Source]

There are two important points to note in this type of model:

  1. The switching stages have to be modeled with a transient simulation and an FFT is needed to predict the circuit’s frequency response
  2. There will be some output resistance and inductance, which are usually the only two components included in most PDN simulations

The fact that the model is linear is what allows a SPICE simulator to predict a frequency response (transfer function) for the VRM circuit. From here you can identify poles that would lead to instability, and this tells you where to begin adding bulk decoupling capacitors in parallel on the output to dampen the transient response. A good strategy here to attempt to achieve a flat impedance is to cycle through capacitance values with a parametric sweep, which will eventually converge on an optimal capacitance value that produces a flat response.

When you’re designing the core regulation circuitry in a VRM, make sure you get the most accurate evaluation of your system functionality with the comprehensive set of simulation tools in PSpice from Cadence. PSpice users can access a powerful SPICE simulator as well as specialty design capabilities like model creation, graphing and analysis tools, and much more.

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