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Pulse-Skip Modulation (PSM) Helps Handle Low Loads

pulse skip modulation

Switching power regulators work by modulating and filtering power delivery to a load, and the most common modulation scheme by far is PWM. By adjusting the duty cycle, the modulator can adjust the output voltage or current, depending on the control mode implemented in a PMIC or gate drive. Another option is pulse skip modulation (PSM), which is sometimes available as a feature in PMICs with PWM.

The use of PSM is not something that is picked as a primary modulation method in a gate driver. Normally, the designer picks PWM or PFM as the main modulation method, and the appropriate PMIC might have PSM implemented as part of its control strategy. If you’re looking for a way to reduce power consumption required to drive a switcher, a PMIC or control strategy with PSM provides one option.

Why Use Pulse Skip Modulation?

PSM is a technique used in switch-mode power supplies where the PWM or PFM driving signal is occasionally skipped. When used to drive the switching stage, specific pulses in the PWM/PFM driving waveform can be momentarily skipped or removed from the pulse train. By eliminating some of the pulses, the switching element will not be driven and will not draw power into the regulator.

Removing a pulse reduces power in two ways:

  • Reduces switching losses that would occur during a pulse

  • Avoids using power to generate a PWM/PFM signal

Overall this helps reduce total power loss during operation. It is typically used in situations where the regulator is delivering a small amount of power to a load, i.e., when the load has high impedance.

Because PSM is not a modulation scheme that is implemented on its own, it must be implemented via an analog control loop with discrete components, or by selecting a gate driver/PMIC/regulator that includes PSM as a feature. An example is the TPS54302 power regulator IC shown below. From the block diagram, we can see that the pulse skipping feature is built into the component and is wired into the control logic. No external programmability is needed to implement the pulse skipping functionality in this component.

pulse skip modulation

In this component, the pulse-skipping threshold is 500 mA. In other words, whenever the output current is less than 500 mA, the device will automatically begin skipping pulses to save power. This feature is an important part of low-power design in addition to monitoring and toggling peripherals in a system.

This type of regulator offers several advantages in terms of power consumption in the gate driver and power consumption in the switcher, both of which also reduce total heat output in low-power states. One of the tradeoffs may be higher EMI in the system due to a transition to discontinuous operation, depending on the PWM/PFM operating frequency range and the amount of inductance in the output current path.

Reduced Switching Loss

The main benefit of using PSM is to reduce the switching losses in the FET. Each time the system drives a FET gate in a switching regulator, it must draw some power into the system. Some power will be lost in a FET’s channel during conduction due to the residual R_ON, even at low load. By eliminating a pulse, these losses are also eliminated. For example, if the PSM strategy eliminates every other pulse, then total switching losses will be reduced by 50%.

Higher EMI

Nothing is free in electronics design, including power savings. The main benefits of power reduction at low loads could potentially be offset by a brief change of the conduction mode into discontinuous mode when the power regulator enters pulse skipping.

When low loads arise, the PSM feature will omit pulses, during which time the inductor current could fall to zero. Essentially, this is like the circuit operating at a lower duty cycle whenever pulses are omitted. No matter how you want to describe it conceptually, the inductor current dropping to zero allows a transient to arise which could translate to conducted or radiated EMI in the circuit.

pulse skip modulation

Comparison of harmonic content in a PSM signal (Left) vs. PWM signal (Right). (Image source)

This can be compensated by using a larger inductor in the circuit as this will help slow down the ripple in the power converter circuit. Although PSM-based power savings are normally desired in small devices, a larger inductance will require a physically larger inductor package to provide greater stability during PSM. This is one of the important design tradeoffs that should be understood when using power regulator ICs with a PSM feature.

No matter what type of power regulator you want to use, you can place and route your power circuits with the best features OrCAD from Cadence. If you’re ready to take even more control over net logic and board layout, you can graduate to Allegro PCB Designer for a more advanced toolset and additional simulation options for systems analysis. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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