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Not just one, there should be a sanity check at every major step in the life of a layout. Some of us fondly remember the Apollo program on the grainy black-and-white TVs of the day. The whole build-up to launch was a long series of steps before the final countdown, Tee minus ten, nine, eight, seven... Liftoff. Looking at "T" as tape-out day and the steps leading up to it as a percentage, we can start at T minus 100 with 100% of the work left to be done.
T - 100
GATE 1 Design kick-off
Stack-up: It starts with defining the materials and geometries and capturing those as a baseline. Via structures, controlled line widths/gaps, minimum hole size, plating and finish specs are the first thing that drive cost and need to be known up front.
T - 99
Your fabricator(s) must be engaged at this point so that they have visibility and material ready for the big day.
T - 95
Outline: Mounting holes, connector orientation, keep-out areas, fiducials, cut-outs, assembly sub-panel, shielding, heatsinks, every mechanical attribute should be covered.
T - 90
You should have enough of a picture here to discuss the time-line and get buy-in from the team. If you're lucky enough to have a Program Manager, they start earning their paycheck right here. They're a huge asset and you need to be tightly coupled.
You manage and own the schedule or it will own you.
T - 85
Library: Ongoing throughout layout process, but heaviest at the beginning. Schematic symbols, footprints, step models all tied together and checked. Checked again by someone else if possible.
Any relevant dimensions on the data sheet should be reflected on the footprint. Yes, that takes time but the board cannot be any better than the underlying symbols. Scrapping boards or waiting while a transposer is created can be the difference success and failure.
T - 80
Net Logic import: There may be some debugging along with the feasibility study as you can finally see the work that lies ahead.
Anticipate 10 or more iterations throughout layout process, often back loaded. Your market window is unlikely to wait for the schematic to be 100% complete so go with what you know.
T - 75
Placement: The first day should be spent on the connectors and the SOC / DDR chipset or whatever piece(s) represents the critical path. Anything that has to be simulated or is otherwise exposed to iteration is fair game. The rest of the placement is paused for initial routing studies. The work done here lays the foundation for all that follows.
T - 70
GATE 2 - Initial placement review:
It's just you, the EE and the ME. Focus on system interfaces and mechanical clearances. Skip this step at your own peril.
T - 65
The outline should be well defined coming out of this gate. You have just enough to get a sense of the overall project. Dial in on your final schedule - either stay the course or make adjustments based on how things went in the review.
T - 60
Power planes: Another chance to optimize the placement as the details come into focus. Ground is flooded and stitched together. The current density/thermal simulations should be closed out by this point.
T - 55
Other Critical Routing: All controlled impedance lines/pairs with proper ground techniques to prove out the placement. Any obvious optimization should be done at this time. You want to be sure you've met your timing budgets or whatever is essential to performance.
T - 50
GATE 3 - Final placement review: You, and a few engineers who focus on SI/PI or the essential requirements The electrical and mechanical constraints should be well defined coming out of this gate. It's beginning to resemble a board.
Congratulations, you're half way there.
T - 40
General fanout, routing and continued placement touch-up. A lot of little problems get solved during this stage. You may have noticed that the line between placement and routing is a bit fuzzy. Deal with it. This is also where an auto-router might be useful.
T - 30
GATE 4 - DRCs and gratuitous ground vias: The schematic and board should be fully functional by this stage. Submit this to the wider team so they can review and comment. Make sure that everyone knows that silence will be construed as acceptance.
T - 25
Changes should be minor beyond this point so as not to affect schedule. If you're getting hit hard with change requests at this stage, you might want to seek management buy-in or intervention. Even if it's going well, send out reminders about the final design review.
T - 20
Clean up non-metal layers and documentation for DFM pre-check. Hopefully, you were able to allocate some time upstream so that most of this was done already. The BOM and the rest of the design collateral should be at the assembly house/ODM by now.
T - 15
Here's the checklist for the layout
- Load the netlist just in case.
- Run whatever reports you need to find design rule violations including opens and shorts, placement interferences, soldermask slivers and so on.
- Tooling holes on the board and/or break-off tabs.
- Fiducial marks for board level and fine-pitch components.
- Selective plating should have its own artwork layer.
- ICT coverage, largest practical pads and spacing, uniform distribution, money and time for the fixture or programming for the flying head.
- There's a dozen other things to eye-ball but you're not inspecting in the quality. That needs to happen upstream.
Now, lets check the fabrication drawing:
- Notes: the fewer the better. Call out your IPC-6012 class and the exceptions to those rules as necessary. It's pretty much self contained aside from soldermask color and various preferences.
- Test coupon
- Assembly sub-panel
- Dimensions and tolerances
- Drill chart
- UL, date code and other vendor marking locations.
- Regulatory requirements: RoHS, certificate of compliance.
- Packing and shipping requirements.
- ESD handling
- Reference documents, BOM, stencil, XY file etc.
- Component outlines
- Reference designators
- Serial number, rev and other labels
- An arrow to indicate the direction of travel.
This is a "What Is" not a "How To" document. Avoid getting tangled up in process control. Once everything is camera-ready, use your output format of choice to export the full design package including a ReadMe.doc
T - 10
DFM release: The vendor has their second look as this would be the same people who gave us the initial stack-up. Right? If not, the foundation could crumble.
T - 5
Incorporate and/or agree to any DFx stipulations from the vendor while a parallel effort goes on at the office to close out the 11th hour improvements.
T - 1
Changes! Call them "improvements" which has a nicer connotation. You tried, but it's just inevitable in something this complex. It would be better if input tapered off, but let’s be real. This is crunch time when you earn your salt.
Circle back to T - 15 if you must
T - 0
GATE 5 OK2FAB. There shouldn’t be many surprises at this point, but another look at connector orientation and other critical items is a must.
T + 1
Put this one to bed in as close to the as-built state as practical. Capture the "tribal knowledge" workarounds, waived DRC's and anything you're likely to forget before the next spin.
T + 2
Put your feet up and crack open a cold one!