Skip to main content

Two Approaches To Ensuring Even Copper Distribution for a Printed Circuit Board

First of all, what is it and why do we want to have copper evenly distributed on our PCB? Look at the material stackup as it alternates between conductor and dielectric material. The goal is to build a mirror-image of copper weights as you work outward from the centerline.

Going beyond specifying alternating shape and route layers, the “greenest” PC board will involve the minimum of etching. It’s intuitive that removing less material will require less time in the solvent tanks. Time is money so that should be reason enough to have all layers biased towards copper fill.

Besides being easier on the equipment, copper-biased design will help maintain an even thickness across the entire board. While we generally get a +/- 10% thickness tolerance from the vendor, we often want a tighter distribution when it comes to the actual PCB thickness.

“The objective, … boards that are all the same thickness and flat as a pancake.”

We basically have to allow the 10% thickness tolerance while aiming to get a 5% variance by providing artwork that makes the most of the raw materials. The more evenly we can design our board, the more consistent the outcome.

This applies to warpage, (twist and bow) as a percentage of the overall length of the board. As an aside, 0.75% is the new 1% as we continue to push the fabricators to deliver flatter boards that support high pin-count surface-mount devices.

The objective, finally, is to end up with printed circuit boards that are all the same thickness and flat as a pancake. (Mmm, pancakes!) The end-result we’re looking for is a high yield through assembly and a low defect rate down the road while saving resources during fabrication. Ok, let’s do it.

High Definition Interconnect (HDI) Strategy

There is quite a bit more latitude when using HDI over traditional through-hole technology. My recommendation is to add a ground fill around the traces once the signal layers have been fully connected. Once the copper flood is in place, it will be more obvious where a session of trace shoving will benefit the routing layers.

We’re looking to isolate differential pairs in their own faraday cages. Clock nets and sense nets are also routed in their own channels for different reasons. Clocks are aggressors while many sense lines are, you know, sensitive to outside influence particularly from clocks and high-speed connections.

Figure 1. Image Credit: Author - Isolating differential pairs and clocks (tinted yellow) are a good way to use copper flood on routing layers.

Once the traces are grouped to maximize copper flood while maintaining ideal inter-trace spacing, it will be relatively easy to stake out ground vias around the perimeter of the shapes on a layer-by-layer basis. The micro-vias used in HDI construction will fit into small spaces and will only span the layers necessary to stitch the local ground planes to the general ground planes on their dedicated layers.

There is always a reason when the PCB is using HDI technology. Invariably, one or more components is a technology driver while other circuits on the board are over-served by such fine-pitch geometry. The micro-vias can still be useful as a via-in-pad solution for the larger power and ground pins on the typical voltage regulators even though they were meant for more mainstream solutions. 

Once there are micro-vias in play, you may as well make the most of them. It is always much faster to make a micro-via vs. a through-hole via. Yes, there are more of them as they sequence through the board one layer at a time but the process is well understood and known to be fairly reliable.

Board With Plated Through-Hole Vias Strategy

Budgetary constraints often compel us to keep it low-tech when it comes to the PCB construction. Of course, there are times when the old-school fabrication is all that is required. The plated through-hole (PTH) process is the most reliable technique in use. We often find it under the hood of our vehicles or on board rockets to be shot into space. Whether we’re talking about the low end or the high end of the cost scale, PTH boards still have a long runway.

The thing is that every via crosses every layer so it’s easy to wind up with too much of a good thing when we attempt to use vias to create thermal paths or faraday cages. The density of the stitching vias can create barriers on power and routing layers that diminish the flow.

Figure 2. Image Credit: Author - Metal loading in locations where too many vias would be disruptive.

In general, the HDI boards are used to manage current density and high-speed transmission lines to a greater extent than their PTH cousins. In low to medium density designs, the space between pins is going to be more relaxed and thus the routing solutions may be simpler.

We’re still going to see a wide variance in metal loading between power, ground and signal layers. In order to prevent the PCB from resembling a potato chip, we want to even out the copper distribution. All of the layers, no matter their function, should have a similar percentage of metalization coverage.

You may be able to get there by flooding copper ground planes on all unused areas. The issue then becomes staking down the perimeter of each shape with vias. If they are left “floating” then the shape is more likely to become a conduit for transferring noise from one place to another.

Ground bounce, ripple, and other signal integrity effects are more common when the ground planes are not well-connected wherever they go. Components, routing busses and power planes may make it difficult to add as many vias as would be necessary for each layer of copper pour.

For this reason, I tend to go for adding non-functional copper in places where ground pour is inadvisable. There can be a fabrication note that spells out the size, shape and spacing of the non-functional copper. Taping out an unbalanced board without a note on the subject will trigger the fab shop into asking permission to add “thieving”.

The fabricators are volunteering to do so in order to meet the IPC requirements for flatness and thickness but I’m sure they would be happier if you lead the way. I don’t want to leave it up to them so I go ahead and create the thieving as part of the artwork rather than relying on a fab-note.

A Final Thought on Implementing Copper Thieving

Have you ever heard of the golden ratio? It’s something found in nature like the chambers of a nautilus shell or a hurricane. It is also favored by architects and graphic designers. That is the geometry I like to use when creating an area of thieving. Making rows of rectangles that are offset to resemble a brick wall is my favorite method but a bunch of little dots will do as well for metal loading. I like to think that the board gets a little more stiffness from the brick wall approach though there is no proof of it.

Figure 3. Image Credit: Deposit Photos - The geometry of the golden ratio is seen in the small rectangle. Numerically, it is close to 1:1.6

The spacing rules will drive the air gaps and the size of the area to be filled will inform the size of the bricks. This filler method can be used on any layer but is most common on component and routing layers. Bottom line: Don’t wait to be asked to even out the metal loading, just go for it either by a design note or getting a little satisfaction with the layout tool.

About the Author

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

Profile Photo of John Burkhert