Ever since the late heavy bombardment, conventional wisdom has held that layer two is a ground plane without end or disruption. Theoretically, anyway. Growing up on processors from Intel, Motorola, TI, and the other pioneers, we hold these truths to be self-evident. A ground plane on layer two was salvation from the tyranny of uncontrolled impedance. Not necessarily so, anymore.
Image Credit: Author - By painting the outer layers in copper, you already have half of the stripline sandwich.
It was about five years ago when Intel gave up Trails and Wells for Lakes as the project names for the 64-bit computing devices. Up to that point, Intel embraced a package design philosophy they called “via-channel”. The pin-pitch was still fairly generous while rows of balls would be strategically depopulated so that there was just enough empty space for fan-out.
Via Channel - The End of the Through-Hole Era
If you did it exactly the way they proposed, the Bay Trail device could be implemented on a normal PCB using through-hole technology. Aside from the areas designated for vias, the thing you would notice is that it has two dice on the substrate, giving it a rectangular footprint rather than a square. It was obvious that a lot of engineering went into enabling low-cost PCBs. In some cases, they would strive for a reference design of 4 layers. Those were the days.
In the real world, the type of memory of some other feature became a technology driver in implementing the supposedly low-tech solution. Meanwhile, the mobile chip business was concentrating elsewhere. Apple, Samsung, Qualcomm and the like were turning out smaller devices with lower power consumption as a side benefit.
Advancing Technology While Containing Costs
Enter SkyLake, the seventh generation. Along with the eight, ninth and tenth gen, the form-factor no longer pretends to have a non-HDI solution. You will be using micro-vias to access many layers. Intel still wants to be frugal though. Noting the reference design and the rather verbose set of application notes, it seems like they’re striving to reduce the number of lamination cycles you will face when putting their newer mobile chips on your board.
The newer generation parts have a pin configuration with two different pitches. The core has a grid of larger pins that are used to supply power and ground. That pin-field is surrounded by a frame of finer pitch signals. Several rows of balls at 0.5 mm center-center all the way around provide about 1000 signal pins on top of the 300 power and ground pads.
Those wide pitch pads that are suited for strapping shunt capacitors across the power and ground grid using the opposite side of the PCB. Even though the application notes call out the use of tiny capacitors, there will be more caps than power/ground pin pairs. It should be said: Get the power and ground pipelines in there early so you can to keep the inductive loops from getting any longer than necessary.
Image Credit: Author - Smaller form factors with many components are poor candidates for this approach.
As usual, the scary XO pins are right along the edge. That generally means that there is some extra plumbing on the device or substrate to make that happen. Pins around the outer edge of the device are the most precious when it comes to ball-mapping. It’s a good chip-team that considers the world beyond silicon. Too many devices brazenly map the PLL or other noisy circuits deep inside the grid. I digress.
Remaining cost-conscious while catching up with the industry means we’re going to have to be creative with the available real estate under the chip. In the immediate vicinity of the SOC, every layer is a routing layer. The style may change to more traditional layer usage once the traces are clear of the high-density area. Impedance will come later.
Architecture For High Density Interconnect
The best case would be a stack-up that went Ground - Signal - Signal - Ground. You’d expect orthogonal routing on the two adjacent signal layers. If traces are going the same way, then try to route Layer 3 over the air gaps of the traces on Layer 2. The same four layers would repeat on the other side of the stack-up with a layer pair for the power distribution network sandwiched in between.
The goal is to route away from the center of the device with a short list of nets that really must have a solid ground foundation for impedance control. The rest of the connections follow according to a hierarchy that you’ll have to work out with the brain trust of your department.
Image Credit: Author - Every design is a compromise.
Most of the time, you’ll be able to help the cause with a placement that accommodates the routing pain points. This strategy applies to smaller devices as well. Use short, direct traces on the outer layer and drop a via to drive a trace of any considerable length.
It’s not unusual to adjust the placement as you go. Using the outer layers as a ground layer means that the component footprints will break up one of the ground planes. Likewise for outer layer routing. Adapting the placement to leverage layer-two routing becomes intuitive with a few iterations.
Keeping the exposed traces short and surrounding the components with a ground plane works wonders for suppressing EMI. Inner layer routing over one solid plane and one broken plane works as long as there’s a thicker band of material between the traces and the subdivided power plane. The core section is a natural place for this technique.
PCIe Cards and similar form factors include solid copper pour on the outer layers as a matter of course. The twin benefits of surface area for thermal dissipation and EMI suppression make it a no-brainer. Take a clue from the established norms and leverage the geometry to create cost-effective layouts that perform to the expectations.