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High-Speed Layout in OrCAD X – It's Simpler Than You Think FAQ

Here are some comprehensive answers to all the questions asked in our recent webinar.

Cross-Section Editor | Constraint Manager | In-Design Workflows | General

Cross-Section Editor

Can we change layer order within the Cross-Section Editor?

Yes, you can always change the layer order in the Cross-Section Editor. However, just be aware of the impact that the stackup change will have on your design.

Does impedance control depend upon the dielectric material?

Yes, variables such as materials, thickness, and more are considered in the stackup calculations. The more accurately you reflect what the fabricator is going to build and use, the closer you'll align with the fabricated results.

Do OrCAD X and Allegro X have the same Cross-Section Editor?

Yes, they do. This ensures that designers can scale their projects from OrCAD X to Allegro X without losing compatibility or needing to redefine the layer stackup.

What is the advantage of a tech file for stackups vs IPC-2581?

A tech file is specific to Cadence whereas IPC-2581 is an intelligent manufacturing format. IPC-2581 does not contain design constraints.

How realistic are the calculations in the Cross-Section Editor with respect to Shield layer when that plane layer is a split plane?

There are many variables in the equations. The closer these variables align with the values your fabricator can provide for the materials, the more accurate they will be. The field solver used has been correlated with numerous testcases.

In the Cross-Section Editor, is it possible to specify a trace width for single ended nets and a separate/second trace width to be used for differential pairs?

No, this is not possible.

Can I add signal integrity values to the Cross-Section chart when I create my fab notes?

This is currently not possible.

Constraint Manager

Is the Constraint Manager within OrCAD X the same as the one in Allegro X?

Yes, OrCAD X and Allegro X share a unified interface for managing design constraints. This allows users to seamlessly transition or scale from OrCAD X to Allegro X tools without needing to learn a new system for managing constraints. It also ensures that constraints can be easily shared and reused across projects. However, please note that OrCAD X offers a more basic set of design rule capabilities, catered towards simpler and less complex designs.

If I wanted to apply rules for a PCIe bus, how would I leverage constraints used in a previous PCB design to another?

This depends on the type of constraints you want to export from your previous design whether it’s Electrical, Physical and/or Spacing. Open up your previous design and go to the Constraint Manager. Within the Constraint Manager menu, click on File > Export. You have the option to select Constraints (.dcfx), which will allow you to bring over all constraints in your previous design. You can then narrow down the ones you want to keep when you import the constraints into your new design, or you have the option to export just the Electrical CSET (.top). Once you have the exported rule file, simply open the Constraint Manager in your new design and click File > Import and select the type of file you're importing.

When will both OrCAD X Presto and OrCAD X PCB Editor have the same level of design rules enabled within the Constraint Manager?

Equalizing capabilities across PCB editors is an ongoing effort with updates occurring in each release. Given the 30 years of technology in the classic editor, it will take time for all of the capabilities to be integrated.

In-Design Workflows

Do I need Sigrity X to run the in-design analysis workflows?

While you do not need a Sigrity X license, you will need to install the Sigrity X software on your system to access the in-design analysis workflows within OrCAD X Professional and above, as they rely on those engines for analysis.

I’m currently encountering an issue with the impedance analysis workflow. Specifically, the results aren’t showing for the differential pair nets that are designed to have 100-ohm impedance traces. How can I resolve this issue?

Make sure you have the display mode set to differential, if that does not work, please file a case with support.

Do the in-design analysis workflows identify the impact of vias on signal integrity, including stubs and ground discontinuities?

Within Analysis Setup you can define if you include the vias in your simulation. The field solver is aware of GND discontinuities as well.

Within the Analysis Workflows Results, if I click on a row in the Impedance or Coupling Table, will it highlight the segment that is offending?

Yes, the table cross probes the selected net and displays it on the design canvas.

Are there any in-design analysis features currently available for capacitor optimization with the aim of achieving power impedance matching?

Yes, within Sigrity X Aurora in-design analysis there is a decap analysis feature.

General

Is the fanout command accessible from a menu or do I have to type it into the console window?

The fanout command is accessible from the floating toolbar menu. Right clicking on the Add Connect icon brings up more options, you will see an icon for Fanout, simply select it to access the command.

Why do we place decoupling capacitors closer to the power pins?

Decoupling capacitors need to be placed as close as possible to the power pins to ensure a stable and clean power supply, minimize inductive effects and filter high-frequency noise within the power delivery network.

Where can I access the previous webinar about constraint management?

You can watch our webinars on-demand here.

Why do we need to length match 50-ohm impedance traces (digital nets)?

Length matching 50-ohm impedance traces, such as data lines in parallel bus interfaces like DDRx, ensures all signals arrive simultaneously at the receiver when the clock triggers, preserving signal integrity, reducing timing skew, and meeting high-speed design requirements.

What is the difference between Allegro X, OrCAD X and Sigrity X?

Allegro X is our enterprise PCB solution. OrCAD X is our PCB solution for smaller design teams, and Sigrity X is our signal and power integrity analysis solution.

What does the tool display when you include the vias and have return GND say 1" away from signal via with say 20ps edge rate?

The via length would be included in any delay constraint violations. If your via is a return path via then it can be specified as a constraint under return path constraints. This would then flag a DRC violation if you don't have a GND via within the required distance.

Normally the dielectric constant is defined only for dielectric materials. Why is it possible to also define it for copper layers in Allegro X?

You can define copper layers within Allegro X because there is dielectric material between the conductors, i.e between the routed traces.

When generating my fab notes, I use the cross-section chart under the manufacture tab. Can I export the line widths and dielectric values in that chart?

This is currently not supported.