High-Speed Layout in OrCAD X – It's Simpler Than You Think FAQ
Here are some comprehensive answers to all the questions asked in our recent webinar.
Cross-Section Editor | Constraint Manager | In-Design Workflows | General
Cross-Section Editor
Yes, you can always change the layer order in the Cross-Section Editor. However, just be aware of the impact that the stackup change will have on your design.
Yes, variables such as materials, thickness, and more are considered in the stackup calculations. The more accurately you reflect what the fabricator is going to build and use, the closer you'll align with the fabricated results.
Yes, they do. This ensures that designers can scale their projects from OrCAD X to Allegro X without losing compatibility or needing to redefine the layer stackup.
A tech file is specific to Cadence whereas IPC-2581 is an intelligent manufacturing format. IPC-2581 does not contain design constraints.
There are many variables in the equations. The closer these variables align with the values your fabricator can provide for the materials, the more accurate they will be. The field solver used has been correlated with numerous testcases.
No, this is not possible.
This is currently not possible.
Constraint Manager
Yes, OrCAD X and Allegro X share a unified interface for managing design constraints. This allows users to seamlessly transition or scale from OrCAD X to Allegro X tools without needing to learn a new system for managing constraints. It also ensures that constraints can be easily shared and reused across projects. However, please note that OrCAD X offers a more basic set of design rule capabilities, catered towards simpler and less complex designs.
This depends on the type of constraints you want to export from your previous design whether it’s Electrical, Physical and/or Spacing. Open up your previous design and go to the Constraint Manager. Within the Constraint Manager menu, click on File > Export. You have the option to select Constraints (.dcfx), which will allow you to bring over all constraints in your previous design. You can then narrow down the ones you want to keep when you import the constraints into your new design, or you have the option to export just the Electrical CSET (.top). Once you have the exported rule file, simply open the Constraint Manager in your new design and click File > Import and select the type of file you're importing.
Equalizing capabilities across PCB editors is an ongoing effort with updates occurring in each release. Given the 30 years of technology in the classic editor, it will take time for all of the capabilities to be integrated.
In-Design Workflows
While you do not need a Sigrity X license, you will need to install the Sigrity X software on your system to access the in-design analysis workflows within OrCAD X Professional and above, as they rely on those engines for analysis.
Make sure you have the display mode set to differential, if that does not work, please file a case with support.
Within Analysis Setup you can define if you include the vias in your simulation. The field solver is aware of GND discontinuities as well.
Yes, the table cross probes the selected net and displays it on the design canvas.
Yes, within Sigrity X Aurora in-design analysis there is a decap analysis feature.
General
The fanout command is accessible from the floating toolbar menu. Right clicking on the Add Connect icon brings up more options, you will see an icon for Fanout, simply select it to access the command.
Decoupling capacitors need to be placed as close as possible to the power pins to ensure a stable and clean power supply, minimize inductive effects and filter high-frequency noise within the power delivery network.
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Length matching 50-ohm impedance traces, such as data lines in parallel bus interfaces like DDRx, ensures all signals arrive simultaneously at the receiver when the clock triggers, preserving signal integrity, reducing timing skew, and meeting high-speed design requirements.
Allegro X is our enterprise PCB solution. OrCAD X is our PCB solution for smaller design teams, and Sigrity X is our signal and power integrity analysis solution.
The via length would be included in any delay constraint violations. If your via is a return path via then it can be specified as a constraint under return path constraints. This would then flag a DRC violation if you don't have a GND via within the required distance.
You can define copper layers within Allegro X because there is dielectric material between the conductors, i.e between the routed traces.
This is currently not supported.