Learn about the advantages of PCIe SerDes architecture.
Gain a greater understanding of the functionality of the PCIe SerDes architecture.
Learn about the changes to design capabilities afforded by the PCIe SerDes architecture.
Storage controller PCIe card with NVMe storage and USB type A and USB type C
In the field of electronics, which encompasses and overlaps several other fields, advancement and evolution are constant. In the area of computing, for instance, innovations typically occur every six months. When you couple this fact with ever-growing demands for efficiency, increasing data rates, and greater demands for reliability, this self-perpetuating cycle does not have an end in sight.
One particular component in use in servers, desktops, laptops, and even gaming consoles, is the PCIe slot. Its evolution and advancements are also a direct correlation to these increasing demands on performance, functionality, and lifecycle.
The PCIe Slot
The Peripheral Component Interconnect Express, or PCIe, is an interface standard utilized to connect high-speed components. We encounter these interfaces on motherboards (PC) in the form of slots. They are typically in use as interfaces for GPUs (graphics cards), SSDs (solid-state drives), and even WiFi cards, to name a few. There are also different versions or configurations of PCIe.
The various physical configurations for PCIe slots include: x1, x4, x8, x16, and x32. The numerical designation indicates the number of lanes the PCIe slot has available, i.e., pathways for data to travel to and from the card. For example, a PCIe (x1) slot utilizes a single lane and moves data, one bit per cycle. A PCIe (x2) slot utilizes two lanes and moves data, two bits per cycle, etc.
In terms of functionality and performance, these designations also indicate a PCIe slot’s performance limitations. For example, if you insert a PCIe (x1) card into a PCIe (x16) slot, the card will function at the lower bandwidth (x1). Likewise, if you insert a PCIe (x8) card in a PCIe (x4) slot, the PCIe (x8) card will function at the bandwidth of the PCIe (x4) slot or half its bandwidth.
The PCIe Generations
PCIe PIPE 5.1 SerDes Architecture
As the demands increase for efficiency, bandwidth, and cost-effectiveness in the design of all devices whose functionality relies on data transmission capabilities, so does the need for the evolution of the technology. Furthermore, PCIe, like its predecessors (PCI and AGP), continues to evolve to keep pace with the current demands. This evolution is giving way to the merging of the PCIe standard with SerDes technology.
The culmination of these two technologies yields a standard currently available called PCIe PIPE 5.1 SerDes. This standard or architecture is a direct result of the demands shaping the advancements in transmission technology. The PCIe PIPE 5.1 SerDes Architecture, in which the PIPE stands for PHY Interface for the PCI Express, is a necessary evolution to match the latest specifications. However, it not only meets the latest specifications, but it also permits scaling for protocol developments in the future.
As you may know, the PHY interface refers to the Physical Layer of the OSI model. In this seven-layer OSI model (computer networking), the physical layer (Layer 1) is not only the first layer but also the lowest layer as well. The physical layer, which can be employed via a PHY chip, defines a means for transmitting raw bits of data over a physical data link, thus connecting network nodes. In summary, this layer specifies the cabling, hardware equipment, wiring, pulses, and frequencies utilized to represent binary signals.
PCIe PIPE 5.1 SerDes Architecture Continued
In today’s technological landscape, we see machine learning and AI briskly infiltrating a wide array of devices. This, of course, drives the re-design of system-on-chip (SoC) designs, thus necessitating increased memory space and greater bandwidth for transferring and processing data. Accompanying these changes is the need for wider buses and higher speed interfaces.
Furthermore, this paves the way for the enhancements we see in the latest PCIe protocol specifications. This also facilitates improvements in PIPE specifications as the preferred PHY interface. The SerDes architecture removes complexities with the PIPE 5 PHY protocol by shifting all of the protocol-specific logic to the controller. Overall, it clarifies the PHY design and permits it to be more easily shared by various protocol stacks. The SerDes architecture for the PIPE interface achieves scalability by presenting several critical changes to the functionality of the Physical Coding Sublayer (PCS) and Media Access Layer (MAC), as well as signaling interface updates.
The following are the principle updates of the PIPE 5.1 specifications besides those brought about by the SerDes architecture.
The Media Access Layer now performs the encoding and decoding of 8b/10b or 128b/130b
Media Access Layer maintains the Elastic Buffer Control
The RxStatus only performs Receiver Detection
RxData is synchronous to the recovered clock RxClk (receive data clock), as presented by PHY
Does not use the RxPolarity field for SerDes architecture
Media Access Control inverts receiver polarity
Media Access Control performs Loopback
Now supports 64-bit data width solely for the SerDes architecture
PIPE Data Widths change from 10, 20, and 40 bits to 8, 16, and 32 bits
The SerDes architecture continues to increase its inclusion into all things data related. With the continuous evolution of the PIPE specifications, it will facilitate the design and verification cycles of complicated PCIe controllers and PHYs to become more time-consuming and intricate.
Close-up PCIe x1 and x16 slot on the computer mainboard
To learn more about implementing PCIe SerDes architecture or leveraging the advantages it offers, visit the Cadence PCB Design and Analysis overview page. Cadence has a full suite of design tools, including Allegro PCB Designer, to help you create designs from verified component models and analyze all aspects of its functionality.
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