SerDes Design: High Speed Electronic Challenges

According to its definition, design is a plan or drawing produced to show the look and function or workings of a building, garment, or other objects before it is built, made, or manufactured. For such a small word, that is a very long-winded definition, but it also alludes to the complexity of the word.

We hear the word almost daily, and the fact is, we see evidence of its meaning all around us. For example, even scheduling your busy workday in a manner that exercises efficiency, in essence, is planning, which is, by definition, designing. Furthermore, designing is in use in the decision making for every decision you make. However, like most things we encounter in our daily lives, there always seem to be obstacles to our plans or full fruition.

Well, that is the same in the field of electronics. For example, I am sure you are familiar with the functionality of a Serializer/Deserializer or SerDes. Those who use them in their designs understand that designing is usually not a straightforward path. In almost all cases, there are corrections, deviations, and reworks, and during this process, there are also guidelines that you must adhere to. Furthermore, these guidelines, results, and the designs themselves also require verification. So, over the next few paragraphs, I will discuss the challenges of designing with SerDes as well as cover the verifications involved in the process.

What is a SerDes?

A SerDes (Serializer/Deserializer) is an integrated circuit or device in use in high-speed communications that converts between serial data and parallel interfaces in either direction. Also, there are a variety of applications and technologies that use a SerDes, for the principal purpose of providing data transmission over a differential or single line by minimizing the number of input/output pins and connections.

In terms of functionality, a SerDes chip enables the transmission between two points that use parallel data over serial streams, thus mitigating the number of data paths required for the data transfer. Also, this reduces the amount of needed connecting pins, thus keeping the wires and connectors small and thin. Furthermore, the transmitter side handles the conversion of parallel data to serial data, whereas the receiver side performs the polar opposite function.

It converts parallel data into serial data so that it can travel over media that doesn’t ordinarily support parallel data. Also, a SerDes can be in use in circumstances in which there is a need to preserve bandwidth.

Designing with a Serializer/Deserializer (SerDes)

Serializer/Deserializer (SerDes) is already emerging as the leading solution in chips where there is a need for high-speed data movement and a limitation in the available I/O. However, like virtually all things, there are side-effects. In the case of SerDes, these side-effects take the form of extreme challenges in terms of designing. Furthermore, these challenges are not going away or getting any easier, especially with the steady increase in the demand for higher speeds in conjunction with the enormous increase in data requirements.

Also, in regards to the benefits, a SerDes affords the conversion of parallel data into serial data, which allows designers to increase the speed of data communication without the need to increase the pin count. However, with the increasing volumes of data, the number of devices (accessing the internet), and the onset of growing Cloud access, the design parameters for a SerDes is also increasing in complexity.

Nevertheless, SerDes is the key to designers and engineers meet this ever-increasing demand for speed and volumes of data. To summarize the totality of what a SerDes represents, it is the perfect convergence of analog precision and analog circuitry.

SerDes and the Design Landscape

The major driving force behind the increasing need for designs that include a SerDes stems from large data centers, where currently, they have throughputs upwards of 100 Gbps. Even with their impressive speeds, there is still urgings to up their performances to 400 Gbps. Not to mention the fact that some are already discussing the possibility of 800Gbps. It is safe to say that these numbers will only increase, which means that the need to accurately design circuits that incorporate SerDes is paramount.

Furthermore, with the onset of artificial intelligence (AI) applications and machine learning, the demand for higher processing speeds and increased parallel processing is definitely on the rise. Also, with the assumed amount of parallel processing facilitated by large data centers, it is not uncommon for them to run out of actual physical space. Which, of course, increases the need for designs that incorporate SerDes.

Also, due to these revelations, the standards from the Optical Internetworking Forum and IEEE are defining even higher data rates on a single lane, thus allowing the aggregation of data to even larger systems. Thereby requiring SerDes technology to increase its level of overall performance and currently, the best way to do that is through the adoption of 4-level pulse-amplitude modulation (PAM4) signaling.

With the ever-increasing demand for SerDes performance, you’ll inevitably see them in more accessible locations too.

The Need for Increased SerDes Performance and Functionality

Today’s demands for higher speeds, now have us seeing (serial) data hitting rates of over 100 Gbps per channel. The signal impairments caused by these increases in bandwidth are forging the need to adopt options like PAM4 to meet those demands. So, how does PAM4 increase a SerDes’s performance? Well, in essence, it doubles the performance rate of the SerDes.

For example, in telecommunications, we compare non-return to zero (NRZ) to PAM4, PAM4 will cut the bandwidth in half for a specified data rate since it transmits two bits in each symbol. Furthermore, it affords a doubling of the bit rate within the channel without doubling the necessary bandwidth.

However, like the rest of our imperfect world, there are trade-offs for this impressive performance increase. PAM4’s ability to transmit multiple symbol levels also makes it susceptible to amplitude noise. Nonetheless, operating at such high frequencies and the capability of operating at half the NRZ Nyquist frequency, still makes PAM4 a better alternative.

Challenges of High-Speed Circuit Designs

One of the many challenges of high-speed designs includes the ever-increasing susceptibility to issues of EM (electromagnetic) crosstalk. Here are some of the major reasons why problems with EM cross-coupling is becoming so significant:

1. Precipitously increasing the use of high-speed interfaces to support the data transmission of faster data rates. Thereby requiring multiple lanes that tend to be in close proximity, thus creating cross-talk issues.

2. The use of higher frequencies that are now more than 2-gigahertz (on-chip) and above 6-gigahertz in 5G applications.

3. Higher integration, multiple radio integration into an SoC, and higher layout density (SoC).

4. Small form factor (packaging) and the extensive use of RDLs (re-distribution layers).

5. The use of 2.5D packaging technology and the use of 3D packaging technology.

In summary, with the advanced packaging styles, the increased clock speeds, and the ever-present demand for reduced (design) areas, our current approach to designing and verifying high-speed IC designs are quickly becoming obsolete.

Design Challenges with SerDes

The challenges of designing with a high-speed SerDes has a general focus on clock distribution (analog clock tree), power consumption, the type of packaging, and the parasitics. Also, there is a focus on the PCB routing, fast digital logic, and support of test modes as well as test patterns. Last but not least, there is a need for compliance with the higher level of the serial protocol.

All of the above challenges need design consideration when integrating into a custom chip. Depending on the requirements and the application, there is the potential to achieve your desired design through alternative solutions, but this usually involves some type of trade-off. Such as a compromise between one or multiple high-speed serial lanes and a slower, yet still fast, parallel bus.

Also, as the frequency increases, issues such as cross talk, jitter, power supply noise, ringing, ISI (intersymbol interference), and ground bounce are all more acute. Furthermore, this also makes signal integrity an even more critical aspect of design architecture. Also, this impacts package design and adds to the design consideration when implementing designs for these tighter electrical performance requirements and higher frequencies.

Careful attention is a requirement for both the high-speed I/Os and the analog supplies within the packages themselves. There is also a need for (package) substrates with designs that utilize EM simulation to verify that the package design meets the essential requirements. Furthermore, this includes S-parameter, impedance, all cross-talk isolation, and supply inductance.

Hopefully SerDes design only gets easier in the future.

SerDes is now and will in the future, provide the added functionality and performance that is in perpetual demand. The onset of 5G only paves the way for 6G, and this need for higher speeds and larger volumes of data will and must continue. The advancement of telecommunications, cellular technology, and PCB design as a whole dictate it.

SerDes design strategies can be implemented with plenty of Cadence’s design and analysis tools. To get you started, Allegro can work through the layout and circuit components of any PCB design as well as work together toward the production and finalization of these designs. 

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.