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Managing Impedance in Your PDN

Key  Takeaways: 

  • Learn about PDN impedance and what it takes to control
  • Understand the utility different software tools can provide for your PDN design process
  • Discover ways to simulate and model PDN impedance properly within PSpice


Managing PDN impedance for a new PCB

This new board needs a carefully designed PDN


PDN impedance is one of those critical concepts in high speed PCBs, but many designers leave it as an afterthought. For components running at 5 V or 3.3 V, you will usually be fine if you use adjacent plane layers and a few decoupling/bypass capacitors on critical components. For advanced designs running with fast edge rates, and when high current is drawn into the PDN, you need to carefully design the PDN to suppress large transients.

With the set of simulation tools in PSpice, you can carefully analyze and tune your PDN impedance spectrum to a target value within the relevant bandwidth for your system. Here’s how you can do this in the frequency domain and the time domain. With the right set of simulation tools, you can take information directly from your circuit schematic and create a useful model for your PDN impedance.

What is PDN Impedance Management?

The target PDN impedance sets an upper limit on the peak impedance value throughout your PDN. The actual PDN impedance will determine the magnitude of any transient ripple waveform on the power bus, which will translate into jitter on the output signal from a high speed IC. When an IC switches, it will draw some current from the power supply, which will propagate as a pulse waveform through the PDN. Parasitics in the PDN and any capacitors will provide some reactance, which creates a transient response in the PDN. The goal of PDN impedance management is to make any transient waveform as small as possible.

The size of any transient ripple waveform on the PDN is a function of the PDN impedance and the transient current that is drawn as an IC switches. Since impedance is a function of frequency, you need to ensure the entire impedance curve throughout the relevant signal bandwidth is below some target value. The relationship between these two is derived from Ohm’s law and is explained in greater detail below.

You can learn more about general PDN management, and the specifics of power integrity, DC and AC power loss, decoupling capacitor placement, and resolving voltage ripple in our available ebook PDN: Gives Your Board Life. PDN management and simulation is not only a specialty but a priority of PSpice, and will surely find strong resolution in any of the problems that may plague your PDN designs. 

Calculating Your PDN Impedance Target

The target PDN impedance sets an upper limit on the peak impedance value throughout your signal bandwidth. As component supply voltages have dropped over time, so have allowed supply voltage ripple values. These ripple values are normally specified as a percentage, and you’ll need to convert this ripple percentage to an impedance target. This can be calculated with the following equation:

arget impedance for managing PDN impedance

Target PDN impedance equation


Note that, in the above equation, the ripple percentage is expressed as a peak-to-peak value, not as a ripple amplitude. This is because ripple is not purely sinusoidal, so it does not make much sense to write ripple in terms of amplitude. One version of the above equation uses a ripple amplitude (assuming a sinusoidal ripple waveform), and a 50% factor is placed in the denominator. Note that the target impedance values calculated with both equations are equal.

As an example, suppose we are using a component with 3.3 V supply voltage and 2% allowed ripple (peak-to-peak). If the maximum peak current an integrated circuit can draw during switching is 0.5 A, then the target impedance is 132 mOhm. Note that this is a magnitude; the PDN can have resistive and reactive components, which will collectively determine the magnitude of any ripple waveform.

When you’re working in a situation where multiple devices on the PDN are switching simultaneously, you need to consider the total current that can be drawn at any given moment. Since the total current drawn at any moment will be larger than the current drawn by an individual IC, this pushes the target PDN impedance to a lower level.

PDN Elements to Examine in a Circuit Simulation

Circuit simulation is the first place to start examining and managing PDN impedance. As impedance varies with frequency, your goal in managing PDN impedance is to calculate the impedance spectrum from DC up to a very high frequency. The PDN impedance should cover the relevant signal bandwidth for your components. This requires considering the following points in a circuit simulation:

  • Capacitor self-resonances: Your decoupling/bypass capacitors on any components have some self-resonance frequency due to their equivalent series resistance (ESR) and equivalent series inductance (ESL). You can get typical values from your desired capacitors by looking at datasheets. Your datasheets will usually show you the self-resonance frequency as well.

  • Interplane capacitance: Your board stackup will determine the capacitance between the power and ground planes in your PDN. This is a parasitic effect, although it is necessary to ensure the PDN in a high speed PCB has sufficient decoupling. By taking advantage of the natural capacitance in your stackup, you can reduce the reliance on discrete decoupling/bypass capacitors. Typical values are ~0.5 pF/sq. mm for a standard thickness 6-layer PCB.

It is important to understand that there are some things a circuit simulation will not tell you. While parasitics in capacitors (ESR and ESL) should always be included, you can’t account for interplane capacitance or other parasitics directly. Instead, you need to account for any parasitics as equivalent circuit elements in your schematic. This requires estimating the plane capacitance, via inductance, and plane loop inductance.


Managing PDN impedance for a new PCB

Structure of a PDN and parasitics that contribute to impedance. [Image source]


Building a PDN Impedance Model as a Circuit Simulation in PSpice

Let’s look at an example PDN with two capacitors. The table shown below accounts for all the relevant impedance elements in this example PDN. The schematic includes two capacitors (assumed SMD) on a copper-filled 10 cm by 5 cm 6-layer board with 1 oz./sq. ft. copper weight. Note that the copper weight determines the R value in the plane section, while the plane area and board thickness determines the interplane capacitance.

The plane inductance can be approximated at 0.5 nH using the plane cross-section, and the inductance of two vias forming the output are set to 1 nH each. The ESR and ESL values for the capacitors can be determined from datasheets.






0.75 Ohms

100 nF

10 nH


2.9 Ohms

22 nF

15 nH


0.5 mOhm

2.5 nF

2.5 nH

Traces (L1 and L2)

0.5 mOhm


5 nH

While you could examine the ripple waveform directly in the time domain, a better way to determine the PDN impedance is to use a frequency sweep. Here, we want to use the Modeling Application utility in Capture CIS to place simulation elements in a schematic. Note that you could use parts from the PSpice Model Library in these simulations if you want to work with specific components. The window below shows a sinusoidal source being defined within Capture CIS.

Sinusoidal source in Capture CIS for PDN impedance management

Defining a sinusoidal source in Capture CIS


Equivalent series LC circuits for the two capacitors and planes can be defined using the Capacitor entry in the PSpice Modeling Application panel. From here, you can enter your true capacitance, ESL, and ESR values for C1 and C2. You can also enter temperature coefficients and voltage-dependent capacitance coefficients (both up to 2nd order). The schematic that will be used to determine the PDN impedance is shown below.

PDN impedance management schematic

Schematic for a model PDN


To run a frequency sweep, create a new simulation profile and define your sweep parameters. Here, you can set the frequency sweep range and whether you want to use a logarithmic or linear scale. Once you run the simulation, PSpice A/D will open automatically, and you will see a blank graph. You can now start adding traces to the graph. Here, we want to calculate the equivalent impedance of the entire PDN throughout the signal bandwidth. For a 1 ns signal, the knee frequency of 350 MHz can be taken as the band edge. The impedance spectrum in this bandwidth is shown below.

PDN impedance management schematic

PDN impedance spectrum


There is a strong resonance at ~138 MHz, which needs to be suppressed if this board is to be used at higher frequencies/edge rates. This arises from a number of sources, namely the coupled resonances between multiple LC sections. There is a range of moderate frequencies where the impedance is quite low.

This should illustrate an important conceptual point about managing PDN impedance: any PDN is basically a very high order LC network. The size of the load and its impedance profile also determine how transients behave on the PDN. The solution here is to adjust the sizes of the capacitors (both C and ESL values) so that the resonances can be shifted to frequencies above the band edge.

If you’re working on managing PDN impedance, you need the best PCB design and analysis software to create your new system. The simulation features in PSpice Simulator for ORCAD and the full suite of analysis tools from Cadence are ideal for managing PDN impedance. You’ll also have access to verified models directly from manufacturers for simulating circuit behavior.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.