High-Speed Serializer/Deserializers: Implementations and Chip Solutions
I am sure that I am not the only one that has a relative or two that more or less functions like an electronic device or component that we see in the field of engineering and electronics. I know it may not immediately register at first, and that is most likely due to you not looking for the correlation.
For example, I have a high-speed sibling that can easily talk to 10 different people in a phone conversation in a span of 30 minutes. Now, I am not judging here, but I do find this a bit excessive. However, this information path does not end there, because, over the next 30 minutes, this same sibling will have conversed with ten more people.
Moreover, the second set of parallel people will receive all of the serial information collected by my sibling from the original ten people. This process will continue as the second group of ten also has information to route. So, let’s see, we have a high-speed transmission of parallel data that is sent to one location and converted into a serial data stream. Now that serial stream of data is converted back to parallel as it is transmitted. It may not be exact, but this indeed resembles the functionality of a Serializer/Deserializer (SerDes).
What is a Serializer/Deserializer?
Serializer/Deserializer is a transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into a serial stream of data that is re-translated into parallel on the receiving end.
In terms of description, a Serializer/Deserializer is a pair of functional blocks commonly in use in high-speed communications to counteract for the limits in the number of inputs and outputs. Furthermore, these blocks convert data between serial data and parallel interfaces in either direction. Hence the term Serializer/Deserializer, more or less, is a reference to the interfaces in use in the various applications and technologies. Regarding implementation, SerDes is primarily in use to provide data transmission over a single line or a differential pair, which in turn, minimizes the number of interconnects and input/output pins.
In summary, a SerDes is a high-speed transmission system that sends signals from the transceiver on one chip to a receiver on another and in the process, converts parallel to serial and back to parallel.
How Does a Serializer/Deserializer Work?
In terms of the build and functionality of a SerDes, it consists of two functional blocks. The two functional blocks that comprise a SerDes are the Parallel In Serial Out (PISO) block (Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (Serial-to-Parallel converter). Furthermore, a SerDes has four distinct architectures: Embedded clock, Parallel clock, Bit interleaved, and 8b/10b.
The PISO block generally has a set of data input lines, input data latches, and a parallel clock input. Also, it uses an external or internal PLL (phase-locked loop) to multiply the incoming parallel clock up to the serial frequency. In its simplest form, a PISO has a single shift register that receives the parallel data once per parallel clock and shifts it out at the higher serial clock rate. Furthermore, some implementations avoid metastability by making use of a double-buffered register during transfers of data between clock domains.
The SIPO block ordinarily has output data latches, a set of data output lines, and a receive clock output. Furthermore, it uses the serial clock recovery technique to recover the receive clock from the data. However, if a SerDes does not transmit a clock, it will use a reference clock to lock the PLL to the correct transmission frequency. Thus, avoiding low harmonic frequencies present in the data stream.
Also, the SIPO block will then divide the incoming clock down to the parallel rate. Note: Some implementations will have two registers in connection, functioning as a double buffer. One register is in use to clock within the serial stream, whereas the other is in use to hold the data for the slower, parallel side.
Other Implementations of Serializer/Deserializer
In certain types of Serializer/Deserializers, there are encoding and decoding blocks in use. The purpose of these encoding and decoding blocks is to place statistical bounds on the rate of signal transitions to allow for more natural clock recovery in the receiver, to provide DC balance, and to provide framing.
Overall, a Serializer/Deserializer can be an IP core integrated into an ASIC or serial bus controller or it can be a stand-alone device.
In either case, a SerDes is a serial transceiver that translates parallel-data into a serial data stream on the transmitter side and converts that serial-data back to parallel on the receiver side.
Optimizing SerDes design will be helpful in moving into a chip-oriented design career.
The Four Serializer/Deserializer Architectures
As I mentioned earlier, a Serializer/Deserializer has four distinct architectures, and they are as follows:
Parallel clock SerDes: The parallel clock SerDes is typically used to serialize a parallel bus input along with the data address and control signals. It sends a serialized stream along with a reference clock. Furthermore, the clock jitter tolerance at the serializer is 5 to 10 PS RMS.
Embedded clock SerDes: An embedded clock SerDes serializes both the data and the clock into a single stream. It transmits one cycle of clock signal first, and then follows up with the data bitstream, thus creating a periodic rising edge at the start of the data bitstream. Since the clock is unambiguously embedded and is recoverable from the bitstream, the serializer’s transmitter clock jitter tolerance is relaxed to between 80 and 120 PS RMS. Furthermore, the reference clock disparity at the Deserializer is approximately ±50000 ppm (i.e., 5%).
8b/10b SerDes: The 8b/10b SerDes maps each data byte to a 10-bit code before serializing the data. Whereas the Deserializer uses the reference clock to monitor the recovered clock from the bitstream. When synthesizing the clock information into the data bitstream, the serializer’s (transmitter) clock jitter tolerance is between 5 and 10 PS RMS, and the reference clock disparity at the Deserializer is at ±100 ppm.
About applications of this particular architecture, the 8b/10b SerDes provides framing, supports DC-balance, and guarantees frequent transitions. Furthermore, the guaranteed transitions also allow a receiver to extract the embedded clock, and the framing is ordinarily at the start of a packet. Overall, the standard 8b/10b SerDes parallel side interfaces have one control line, one clock line, and 8 data lines.
Bit interleaved SerDes: The Bit interleaved SerDes multiplexes several slower serial data streams into faster serial streams, whereas the receiver de-multiplexes the faster bitstreams back to slower streams.
The Increasing Demand for Serializer/Deserializers
As I am sure you are aware, a SerDes circuit converts parallel data or multiple streams of data into a serial, one bit, stream of data before transmitting over a high-speed connection, like in the case of low-voltage differential signaling (LVDS).
Whether it is PCI Express, XAUI, or SATA, SerDes is emerging as the primary solution in chips where there is a need for high-speed data movement in conjunction with a limitation in the number of inputs and outputs. However, due to the increasing rise in speeds to offset the massive increases in data, designs using the technology are becoming expressively more challenging.
Nonetheless, as the demand for volume and data increases, so does the number of devices that connect to the internet and the cloud. Which, in turn, increases the demand to move more information faster. This overall increase in demand is ultimately what makes SerDes indispensable and yet increases the complexity of its designs.
What do you anticipate the demand for data will look like in 2025? 2040?
SerDes is the Q point of analog precision and analog circuitry, and its demand only stands to increase. Although the majority of the requirements for high-speed SerDes comes from large data centers, it is not exclusive. Even now, the standards from IEEE and others are defining increasingly higher data rates on a single lane, with no end in sight. The SerDes technology is currently poised to move its performance to the next level, and as demands continue, it will be a must.
Have your designers and production teams working together towards implementing Serializer/Deserializers in all of your PCB designs with Cadence’s suite of design and analysis tools. Beginning with layout and through analysis phases, working with Allegro will be sure to help mitigate and resolve any potential design difficulties encountered.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.